Assert statement for verification in VHDL - Mini Project: Build & Apply

Using Assert Statement for Verification in VHDL

📖 Scenario: You are designing a simple digital circuit in VHDL that adds two 4-bit numbers. To ensure your design works correctly, you want to use assert statements to verify the output during simulation.

🎯 Goal: Build a VHDL testbench that uses assert statements to check if the sum output of your adder matches the expected result for given inputs.

📋 What You'll Learn

Create signals for inputs and output

Add a configuration signal for test values

Write an assert statement to verify the output

Print a message when the assertion fails

💡 Why This Matters

🌍 Real World

Using assert statements helps catch errors early in digital circuit design by verifying expected behavior during simulation.

💼 Career

Verification engineers and digital designers use assert statements to ensure their hardware designs work correctly before manufacturing.

1

DATA SETUP: Declare input and output signals

Declare signals a and b as 4-bit std_logic_vector inputs, and sum as a 5-bit std_logic_vector output in your VHDL testbench.

VHDL

-- Declare signals a, b as std_logic_vector(3 downto 0) and sum as std_logic_vector(4 downto 0)
-- Your code here

Need a hint?

Use signal keyword and specify the bit ranges exactly as shown.

2

CONFIGURATION: Assign test values to inputs

Assign the value "0011" to signal a and "0101" to signal b in your testbench process.

VHDL

signal a : std_logic_vector(3 downto 0);
signal b : std_logic_vector(3 downto 0);
signal sum : std_logic_vector(4 downto 0);

-- Assign "0011" to a and "0101" to b
-- Your code here

Need a hint?

Use signal assignment with <= and double quotes for bit vectors.

3

CORE LOGIC: Write an assert statement to verify the sum

Write an assert statement that checks if sum equals "01000". If not, display the message "Sum is incorrect" with severity error.

VHDL

signal a : std_logic_vector(3 downto 0);
signal b : std_logic_vector(3 downto 0);
signal sum : std_logic_vector(4 downto 0);

begin
    a <= "0011";
    b <= "0101";

-- Write assert statement to check sum = "01000"
-- Your code here

Need a hint?

Use assert condition report message severity level; syntax.

4

OUTPUT: Display the assertion result

Add a report statement to print "Test completed" after the assert statement.

VHDL

signal a : std_logic_vector(3 downto 0);
signal b : std_logic_vector(3 downto 0);
signal sum : std_logic_vector(4 downto 0);

begin
    a <= "0011";
    b <= "0101";

    assert sum = "01000"
    report "Sum is incorrect"
    severity error;

-- Add report statement to print "Test completed"
-- Your code here

Need a hint?

Use report "message"; to print messages in VHDL.