Assert statement for verification in VHDL - Mini Project: Build & Apply

Using Assert Statement for Verification in VHDL

📖 Scenario: You are designing a simple digital circuit in VHDL that adds two 4-bit numbers. To ensure your design works correctly, you want to use assert statements to verify the output during simulation.

🎯 Goal: Build a VHDL testbench that uses assert statements to check if the sum output of your adder matches the expected result for given inputs.

📋 What You'll Learn

Create signals for inputs and output

Add a configuration signal for test values

Write an assert statement to verify the output

Print a message when the assertion fails

💡 Why This Matters

🌍 Real World

Using assert statements helps catch errors early in digital circuit design by verifying expected behavior during simulation.

💼 Career

Verification engineers and digital designers use assert statements to ensure their hardware designs work correctly before manufacturing.

1

DATA SETUP: Declare input and output signals

Declare signals a and b as 4-bit std_logic_vector inputs, and sum as a 5-bit std_logic_vector output in your VHDL testbench.

VHDL

-- Declare signals a, b as std_logic_vector(3 downto 0) and sum as std_logic_vector(4 downto 0)
-- Your code here

Hint

Use signal keyword and specify the bit ranges exactly as shown.

2

CONFIGURATION: Assign test values to inputs

Assign the value "0011" to signal a and "0101" to signal b in your testbench process.

VHDL

signal a : std_logic_vector(3 downto 0);
signal b : std_logic_vector(3 downto 0);
signal sum : std_logic_vector(4 downto 0);

-- Assign "0011" to a and "0101" to b
-- Your code here

Hint

Use signal assignment with <= and double quotes for bit vectors.

3

CORE LOGIC: Write an assert statement to verify the sum

Write an assert statement that checks if sum equals "01000". If not, display the message "Sum is incorrect" with severity error.

VHDL

signal a : std_logic_vector(3 downto 0);
signal b : std_logic_vector(3 downto 0);
signal sum : std_logic_vector(4 downto 0);

begin
    a <= "0011";
    b <= "0101";

-- Write assert statement to check sum = "01000"
-- Your code here

Hint

Use assert condition report message severity level; syntax.

4

OUTPUT: Display the assertion result

Add a report statement to print "Test completed" after the assert statement.

VHDL

signal a : std_logic_vector(3 downto 0);
signal b : std_logic_vector(3 downto 0);
signal sum : std_logic_vector(4 downto 0);

begin
    a <= "0011";
    b <= "0101";

    assert sum = "01000"
    report "Sum is incorrect"
    severity error;

-- Add report statement to print "Test completed"
-- Your code here

Hint

Use report "message"; to print messages in VHDL.

Practice

1. What is the main purpose of the assert statement in VHDL?

easy

A. To check conditions during simulation and report errors

B. To declare variables in the design

C. To assign values to signals

D. To create loops in the code

Solution

1. Step 1: Understand the role of assert in VHDL

   The assert statement is used to verify conditions during simulation, helping catch errors early.

2. Step 2: Compare with other options

   Other options describe unrelated tasks: declaring variables, assigning signals, or looping.

3. Final Answer:

   To check conditions during simulation and report errors -> Option A

4. Quick Check:

   Assert checks conditions = To check conditions during simulation and report errors [OK]

Hint: Assert is for checking conditions during simulation [OK]

Common Mistakes:

• Confusing assert with signal assignment
• Thinking assert declares variables
• Assuming assert creates loops

2. Which of the following is the correct syntax for an assert statement in VHDL?

easy

A. assert condition, "message", severity level;

B. assert (condition) then report "message" severity level;

C. assert condition report "message" severity level;

D. assert condition report "message" severity level

Solution

1. Step 1: Recall correct assert syntax

   The correct syntax is: assert condition report "message" severity level; with a semicolon at the end.

2. Step 2: Check each option

   assert condition report "message" severity level; matches exactly. assert (condition) then report "message" severity level; has incorrect 'then'. assert condition, "message", severity level; uses commas incorrectly. assert condition report "message" severity level misses the semicolon.

3. Final Answer:

   assert condition report "message" severity level; -> Option C

4. Quick Check:

   Correct assert syntax ends with semicolon [OK]

Hint: Remember assert ends with semicolon and uses 'report' keyword [OK]

Common Mistakes:

• Omitting semicolon at the end
• Using commas instead of keywords
• Adding 'then' after condition

3. What will be the output during simulation for the following VHDL code snippet?

signal x : integer := 5;
begin
  assert x > 10 report "Value too low" severity warning;
end;

medium

A. Simulation stops with error

B. Warning message: "Value too low" is displayed

C. No message is displayed, simulation continues silently

D. Syntax error due to missing semicolon

Solution

1. Step 1: Evaluate the assert condition

   The condition x > 10 is false since x = 5.

2. Step 2: Understand severity level effect

   Severity is warning, so simulation shows a warning message but continues.

3. Final Answer:

   Warning message: "Value too low" is displayed -> Option B

4. Quick Check:

   False condition + warning severity = warning message [OK]

Hint: False assert with warning shows message but continues [OK]

Common Mistakes:

• Thinking simulation stops on warning severity
• Ignoring the severity level
• Assuming no message if condition false

4. Identify the error in this VHDL assert statement:

assert (a = b) report "Mismatch" severity error

medium

A. Missing semicolon at the end

B. Incorrect use of parentheses around condition

C. Wrong severity level keyword

D. Missing report keyword

Solution

1. Step 1: Check syntax completeness

   The assert statement must end with a semicolon; it is missing here.

2. Step 2: Verify other parts

   Parentheses around condition are allowed, severity keyword is correct, and report keyword is present.

3. Final Answer:

   Missing semicolon at the end -> Option A

4. Quick Check:

   Assert statements end with semicolon [OK]

Hint: Always end assert statements with semicolon [OK]

Common Mistakes:

• Forgetting semicolon
• Thinking parentheses are not allowed
• Confusing severity keywords

5. You want to verify that a signal data_valid is always true during simulation. Which assert statement correctly stops simulation on failure and shows an error message?

hard

A. assert data_valid report "Data invalid" severity critical;

B. assert data_valid report "Data invalid" severity warning;

C. assert not data_valid report "Data invalid" severity note;

D. assert data_valid report "Data invalid" severity error;

Solution

1. Step 1: Understand severity levels for stopping simulation

   Severity error stops simulation and reports an error message.

2. Step 2: Analyze each option

   assert data_valid report "Data invalid" severity warning; uses warning (does not stop). assert data_valid report "Data invalid" severity error; uses error (correct). assert not data_valid report "Data invalid" severity note; negates condition and uses note (no stop). assert data_valid report "Data invalid" severity critical; uses critical which is not a valid severity.

3. Final Answer:

   assert data_valid report "Data invalid" severity error; -> Option D

4. Quick Check:

   Error severity stops simulation = assert data_valid report "Data invalid" severity error; [OK]

Hint: Use severity error to stop simulation on assert failure [OK]

Common Mistakes:

• Using warning instead of error severity
• Negating condition incorrectly
• Using invalid severity keywords