Why combinational design is the VHDL foundation - Test Your Understanding

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a combinational process sensitive to inputs a and b.

VHDL

process([1])
begin
  y <= a and b;
end process;

Drag options to blanks, or click blank then click option'

Areset

Bclk

Ca, b

Dy

Attempts:

3 left

💡 Hint

Common Mistakes

Using clock or reset signals in sensitivity list for combinational logic.

Leaving sensitivity list empty.

The process must be sensitive to inputs a and b to model combinational logic.

2fill in blank

medium

Complete the code to assign output y as the OR of inputs a and b.

VHDL

y <= a [1] b;

Drag options to blanks, or click blank then click option'

Aand

Bor

Cnand

Dxor

Attempts:

3 left

💡 Hint

Common Mistakes

Using AND instead of OR.

Using NAND or XOR which change logic behavior.

The OR operator combines inputs so output is high if either input is high.

3fill in blank

hard

Fix the error in the process sensitivity list for combinational logic.

VHDL

process([1])
begin
  y <= a xor b;
end process;

Drag options to blanks, or click blank then click option'

Aclk

Breset

Cy

Da, b

Attempts:

3 left

💡 Hint

Common Mistakes

Including clock or reset in sensitivity list for combinational logic.

Omitting inputs from sensitivity list.

Combinational processes must be sensitive to all inputs that affect output, here a and b.

4fill in blank

hard

Fill both blanks to complete the combinational assignment and sensitivity list.

VHDL

process([1])
begin
  y <= a [2] b;
end process;

Drag options to blanks, or click blank then click option'

Aa, b

Band

Cor

Dclk

Attempts:

3 left

💡 Hint

Common Mistakes

Using clock in sensitivity list for combinational logic.

Using OR instead of AND when AND is required.

The sensitivity list must include inputs a and b, and the output is assigned using the AND operator.

5fill in blank

hard

Fill all three blanks to create a combinational process that outputs y as NAND of a and b.

VHDL

process([1])
begin
  y <= a [2] b;
  y <= not (a and b) when [3] else y;
end process;

Drag options to blanks, or click blank then click option'

Aa, b

Band

Ctrue

Dclk

Attempts:

3 left

💡 Hint

Common Mistakes

Including clock in sensitivity list.

Not inverting output correctly.

Using 'false' instead of 'true' in conditional assignment.

The sensitivity list includes inputs a and b. Output y is assigned the AND of a and b, then inverted when true (always), creating NAND logic.

Practice

1. Why is combinational design considered the foundation of VHDL?

easy

A. Because it models logic where outputs depend only on current inputs without memory

B. Because it stores data for future use

C. Because it controls the timing of signals

D. Because it handles communication between devices

Solution

1. Step 1: Understand combinational logic basics

   Combinational logic circuits produce outputs based solely on current inputs, without storing any past information.

2. Step 2: Relate to VHDL foundation

   VHDL models hardware behavior, and combinational design is the simplest form, forming the base for more complex designs.

3. Final Answer:

   Because it models logic where outputs depend only on current inputs without memory -> Option A

4. Quick Check:

   Combinational logic = output depends only on current inputs [OK]

Hint: Combinational means no memory, output depends on inputs only [OK]

Common Mistakes:

• Confusing combinational with sequential logic
• Thinking combinational stores data
• Assuming timing control is combinational's role

2. Which of the following is the correct VHDL syntax to describe a combinational process?

easy

A. process(clk) begin if rising_edge(clk) then output <= input; end if; end process;

B. process(input1, input2) begin output <= input1 and input2; end process;

C. process(reset) begin output <= '0'; end process;

D. process(clk, reset) begin if reset = '1' then output <= '0'; end if; end process;

Solution

1. Step 1: Identify combinational process sensitivity list

   Combinational processes list all inputs that affect outputs in the sensitivity list, without clock signals.

2. Step 2: Check each option

   process(input1, input2) begin output <= input1 and input2; end process; uses inputs in sensitivity list and assigns output directly, matching combinational logic style.

3. Final Answer:

   process(input1, input2) begin output <= input1 and input2; end process; -> Option B

4. Quick Check:

   Combinational process sensitivity list = inputs only [OK]

Hint: Combinational process sensitivity list has inputs, no clock [OK]

Common Mistakes:

• Including clock signals in combinational process
• Using if rising_edge in combinational logic
• Missing inputs in sensitivity list

3. Given this VHDL code snippet, what is the output when input1 = '1' and input2 = '0'?

process(input1, input2)
begin
  output <= input1 or input2;
end process;

medium

A. '0'

B. Error

C. Undefined

D. '1'

Solution

1. Step 1: Understand the logic operation

   The process assigns output as the logical OR of input1 and input2.

2. Step 2: Calculate output for given inputs

   input1 = '1', input2 = '0', so '1' OR '0' = '1'.

3. Final Answer:

   '1' -> Option D

4. Quick Check:

   1 OR 0 = 1 [OK]

Hint: OR gate outputs 1 if any input is 1 [OK]

Common Mistakes:

• Confusing OR with AND operation
• Assuming output is '0' when one input is '1'
• Thinking output is undefined without clock

4. Identify the error in this VHDL combinational process:

process(a, b)
begin
  if a = '1' then
    y <= '1';
  elsif b = '1' then
    y <= '0';
  end if;
end process;

medium

A. Missing else clause causing latch inference

B. Incorrect sensitivity list

C. Wrong signal assignment operator

D. Using clock signal in combinational process

Solution

1. Step 1: Analyze conditional branches

   The process assigns y only when a='1' or b='1', but no assignment if both are '0'.

2. Step 2: Understand latch inference

   Missing else means y keeps previous value, causing unintended latch (memory) behavior in combinational logic.

3. Final Answer:

   Missing else clause causing latch inference -> Option A

4. Quick Check:

   All paths must assign output in combinational process [OK]

Hint: Always assign outputs in all if-else branches [OK]

Common Mistakes:

• Ignoring latch inference from incomplete assignments
• Confusing sensitivity list errors with logic errors
• Thinking signal assignment operator is wrong

5. You want to design a combinational circuit in VHDL that outputs '1' only when exactly one of the three inputs a, b, or c is '1'. Which VHDL expression correctly implements this?

hard

A. output <= a or b or c;

B. output <= a and b and c;

C. output <= (a and not b and not c) or (not a and b and not c) or (not a and not b and c);

D. output <= (a and b) or (b and c) or (a and c);

Solution

1. Step 1: Understand the requirement

   Output is '1' only if exactly one input is '1', meaning one true and two false inputs.

2. Step 2: Analyze each option

   output <= (a and not b and not c) or (not a and b and not c) or (not a and not b and c); checks each input being '1' while others are '0', matching exactly one true input condition.

3. Final Answer:

   output <= (a and not b and not c) or (not a and b and not c) or (not a and not b and c); -> Option C

4. Quick Check:

   Exactly one input true = output <= (a and not b and not c) or (not a and b and not c) or (not a and not b and c); [OK]

Hint: Exactly one true means one input true, others false [OK]

Common Mistakes:

• Using OR of inputs (any true) instead of exactly one
• Using AND of inputs (all true) instead of exactly one
• Using pairs ANDed (two true) instead of one true