Why combinational design is the VHDL foundation - Test Your Understanding

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a combinational process sensitive to inputs a and b.

VHDL

process([1])
begin
  y <= a and b;
end process;

Drag options to blanks, or click blank then click option'

Areset

Bclk

Ca, b

Dy

Attempts:

3 left

💡 Hint

Common Mistakes

Using clock or reset signals in sensitivity list for combinational logic.

Leaving sensitivity list empty.

The process must be sensitive to inputs a and b to model combinational logic.

2fill in blank

medium

Complete the code to assign output y as the OR of inputs a and b.

VHDL

y <= a [1] b;

Drag options to blanks, or click blank then click option'

Aand

Bor

Cnand

Dxor

Attempts:

3 left

💡 Hint

Common Mistakes

Using AND instead of OR.

Using NAND or XOR which change logic behavior.

The OR operator combines inputs so output is high if either input is high.

3fill in blank

hard

Fix the error in the process sensitivity list for combinational logic.

VHDL

process([1])
begin
  y <= a xor b;
end process;

Drag options to blanks, or click blank then click option'

Aclk

Breset

Cy

Da, b

Attempts:

3 left

💡 Hint

Common Mistakes

Including clock or reset in sensitivity list for combinational logic.

Omitting inputs from sensitivity list.

Combinational processes must be sensitive to all inputs that affect output, here a and b.

4fill in blank

hard

Fill both blanks to complete the combinational assignment and sensitivity list.

VHDL

process([1])
begin
  y <= a [2] b;
end process;

Drag options to blanks, or click blank then click option'

Aa, b

Band

Cor

Dclk

Attempts:

3 left

💡 Hint

Common Mistakes

Using clock in sensitivity list for combinational logic.

Using OR instead of AND when AND is required.

The sensitivity list must include inputs a and b, and the output is assigned using the AND operator.

5fill in blank

hard

Fill all three blanks to create a combinational process that outputs y as NAND of a and b.

VHDL

process([1])
begin
  y <= a [2] b;
  y <= not (a and b) when [3] else y;
end process;

Drag options to blanks, or click blank then click option'

Aa, b

Band

Ctrue

Dclk

Attempts:

3 left

💡 Hint

Common Mistakes

Including clock in sensitivity list.

Not inverting output correctly.

Using 'false' instead of 'true' in conditional assignment.

The sensitivity list includes inputs a and b. Output y is assigned the AND of a and b, then inverted when true (always), creating NAND logic.