Why combinational design is the VHDL foundation - See It in Action

Why combinational design is the VHDL foundation

📖 Scenario: You are learning VHDL, a language used to describe digital circuits. Combinational design is the base for many digital systems because it defines outputs based only on current inputs, without memory.

🎯 Goal: Build a simple combinational logic circuit in VHDL that outputs the AND of two inputs. This will show why combinational design is the foundation of VHDL.

📋 What You'll Learn

Create a VHDL entity with two inputs and one output

Define a signal that represents the AND of the inputs

Use a concurrent assignment to implement combinational logic

Print the output signal in a testbench

💡 Why This Matters

🌍 Real World

Combinational logic is used in digital circuits like adders, multiplexers, and control units.

💼 Career

Understanding combinational design is essential for hardware engineers and FPGA developers working with VHDL.

1

Create the VHDL entity with inputs and output

Write a VHDL entity called AndGate with two inputs A and B of type std_logic, and one output Y of type std_logic.

VHDL

entity AndGate is
    Port (
        A : in std_logic;
        B : in std_logic;
        Y : out std_logic
    );
end AndGate;

-- Your code here

Hint

Define the entity with inputs and output ports exactly as named.

2

Add the architecture with a signal for AND operation

Write an architecture called Behavioral for AndGate. Inside it, declare a signal and_result of type std_logic.

VHDL

entity AndGate is
    Port (
        A : in std_logic;
        B : in std_logic;
        Y : out std_logic
    );
end AndGate;

architecture Behavioral of AndGate is
    signal and_result : std_logic;
begin
-- Your code here

Hint

Declare the architecture and the signal inside it.

3

Implement combinational logic with concurrent assignment

Inside the Behavioral architecture, assign and_result to the AND of A and B using a concurrent signal assignment. Then assign Y to and_result.

VHDL

entity AndGate is
    Port (
        A : in std_logic;
        B : in std_logic;
        Y : out std_logic
    );
end AndGate;

architecture Behavioral of AndGate is
    signal and_result : std_logic;
begin
    -- Your code here

Hint

Use concurrent signal assignments to implement the AND logic.

4

Create a testbench to display the output

Write a simple testbench entity and architecture that instantiates AndGate. Set inputs A and B to '1' and '0' respectively, then print the output Y using report statement.

VHDL

entity AndGate is
    Port (
        A : in std_logic;
        B : in std_logic;
        Y : out std_logic
    );
end AndGate;

architecture Behavioral of AndGate is
    signal and_result : std_logic;
begin
    and_result <= A and B;
    Y <= and_result;
end Behavioral;

-- Your testbench code here

Hint

Instantiate the AndGate and use a process to print the output after setting inputs.

Practice

1. Why is combinational design considered the foundation of VHDL?

easy

A. Because it models logic where outputs depend only on current inputs without memory

B. Because it stores data for future use

C. Because it controls the timing of signals

D. Because it handles communication between devices

Solution

1. Step 1: Understand combinational logic basics

   Combinational logic circuits produce outputs based solely on current inputs, without storing any past information.

2. Step 2: Relate to VHDL foundation

   VHDL models hardware behavior, and combinational design is the simplest form, forming the base for more complex designs.

3. Final Answer:

   Because it models logic where outputs depend only on current inputs without memory -> Option A

4. Quick Check:

   Combinational logic = output depends only on current inputs [OK]

Hint: Combinational means no memory, output depends on inputs only [OK]

Common Mistakes:

• Confusing combinational with sequential logic
• Thinking combinational stores data
• Assuming timing control is combinational's role

2. Which of the following is the correct VHDL syntax to describe a combinational process?

easy

A. process(clk) begin if rising_edge(clk) then output <= input; end if; end process;

B. process(input1, input2) begin output <= input1 and input2; end process;

C. process(reset) begin output <= '0'; end process;

D. process(clk, reset) begin if reset = '1' then output <= '0'; end if; end process;

Solution

1. Step 1: Identify combinational process sensitivity list

   Combinational processes list all inputs that affect outputs in the sensitivity list, without clock signals.

2. Step 2: Check each option

   process(input1, input2) begin output <= input1 and input2; end process; uses inputs in sensitivity list and assigns output directly, matching combinational logic style.

3. Final Answer:

   process(input1, input2) begin output <= input1 and input2; end process; -> Option B

4. Quick Check:

   Combinational process sensitivity list = inputs only [OK]

Hint: Combinational process sensitivity list has inputs, no clock [OK]

Common Mistakes:

• Including clock signals in combinational process
• Using if rising_edge in combinational logic
• Missing inputs in sensitivity list

3. Given this VHDL code snippet, what is the output when input1 = '1' and input2 = '0'?

process(input1, input2)
begin
  output <= input1 or input2;
end process;

medium

A. '0'

B. Error

C. Undefined

D. '1'

Solution

1. Step 1: Understand the logic operation

   The process assigns output as the logical OR of input1 and input2.

2. Step 2: Calculate output for given inputs

   input1 = '1', input2 = '0', so '1' OR '0' = '1'.

3. Final Answer:

   '1' -> Option D

4. Quick Check:

   1 OR 0 = 1 [OK]

Hint: OR gate outputs 1 if any input is 1 [OK]

Common Mistakes:

• Confusing OR with AND operation
• Assuming output is '0' when one input is '1'
• Thinking output is undefined without clock

4. Identify the error in this VHDL combinational process:

process(a, b)
begin
  if a = '1' then
    y <= '1';
  elsif b = '1' then
    y <= '0';
  end if;
end process;

medium

A. Missing else clause causing latch inference

B. Incorrect sensitivity list

C. Wrong signal assignment operator

D. Using clock signal in combinational process

Solution

1. Step 1: Analyze conditional branches

   The process assigns y only when a='1' or b='1', but no assignment if both are '0'.

2. Step 2: Understand latch inference

   Missing else means y keeps previous value, causing unintended latch (memory) behavior in combinational logic.

3. Final Answer:

   Missing else clause causing latch inference -> Option A

4. Quick Check:

   All paths must assign output in combinational process [OK]

Hint: Always assign outputs in all if-else branches [OK]

Common Mistakes:

• Ignoring latch inference from incomplete assignments
• Confusing sensitivity list errors with logic errors
• Thinking signal assignment operator is wrong

5. You want to design a combinational circuit in VHDL that outputs '1' only when exactly one of the three inputs a, b, or c is '1'. Which VHDL expression correctly implements this?

hard

A. output <= a or b or c;

B. output <= a and b and c;

C. output <= (a and not b and not c) or (not a and b and not c) or (not a and not b and c);

D. output <= (a and b) or (b and c) or (a and c);

Solution

1. Step 1: Understand the requirement

   Output is '1' only if exactly one input is '1', meaning one true and two false inputs.

2. Step 2: Analyze each option

   output <= (a and not b and not c) or (not a and b and not c) or (not a and not b and c); checks each input being '1' while others are '0', matching exactly one true input condition.

3. Final Answer:

   output <= (a and not b and not c) or (not a and b and not c) or (not a and not b and c); -> Option C

4. Quick Check:

   Exactly one input true = output <= (a and not b and not c) or (not a and b and not c) or (not a and not b and c); [OK]

Hint: Exactly one true means one input true, others false [OK]

Common Mistakes:

• Using OR of inputs (any true) instead of exactly one
• Using AND of inputs (all true) instead of exactly one
• Using pairs ANDed (two true) instead of one true