Why combinational design is the VHDL foundation - Challenge Your Understanding

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of a simple combinational process

What is the output of the following VHDL process when inputs A = '1' and B = '0'?

VHDL

process(A, B)
begin
  if A = '1' and B = '1' then
    Y <= '1';
  else
    Y <= '0';
  end if;
end process;

A Y = '1'

B Y = 'Z' (high impedance)

C Y = '0'

D Y retains previous value

💡 Hint

Think about the condition and the input values.

Since B is '0', the condition A = '1' and B = '1' is false, so Y is assigned '0'.

🧠 Conceptual

intermediate

Why combinational logic is fundamental in VHDL

Why is combinational design considered the foundation of VHDL?

A Because it only works with analog signals.

B Because it requires clock signals to operate correctly.

C Because it uses sequential statements exclusively.

D Because it models circuits without memory elements, making behavior predictable and simple to simulate.

💡 Hint

Think about what combinational logic means in hardware.

Combinational logic produces outputs based only on current inputs without memory, making it easy to model and simulate in VHDL.

🔧 Debug

advanced

Identify the error in combinational process sensitivity list

What error will occur with this VHDL process and why? process(clk) begin Y <= A and B; end process;

VHDL

process(clk)
begin
  Y <= A and B;
end process;

A No error; process works fine as is.

B Y will not update correctly because A and B are missing from the sensitivity list.

C Syntax error due to missing semicolon after Y assignment.

D Runtime error because clk is not used inside the process.

💡 Hint

Consider what signals must be in the sensitivity list for combinational logic.

For combinational processes, all input signals used must be in the sensitivity list to update outputs correctly.

📝 Syntax

advanced

Correct syntax for combinational assignment

Which option shows the correct VHDL syntax for a combinational assignment of Y as AND of A and B?

A Y <= A and B;

B Y = A and B;

C Y := A and B;

D Y == A and B;

💡 Hint

Remember the assignment operator in VHDL for signals.

In VHDL, signal assignment uses '<=' operator, not '=', ':=', or '=='.

🚀 Application

expert

Number of output changes in combinational logic

Given the following VHDL combinational process, how many times will output Y change if inputs A and B cycle through all combinations (00, 01, 10, 11) once?

VHDL

process(A, B)
begin
  Y <= A xor B;
end process;

A 2 times

B 4 times

C 3 times

D 1 time

💡 Hint

Trace output Y for each input combination change.

Y changes whenever A xor B changes. Cycling through 00(0)->01(1) change, 01(1)->10(1) no change, 10(1)->11(0) change. Total 2 changes.