Why combinational design is the VHDL foundation - Challenge Your Understanding

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of a simple combinational process

What is the output of the following VHDL process when inputs A = '1' and B = '0'?

VHDL

process(A, B)
begin
  if A = '1' and B = '1' then
    Y <= '1';
  else
    Y <= '0';
  end if;
end process;

A Y = '1'

B Y = 'Z' (high impedance)

C Y = '0'

D Y retains previous value

💡 Hint

Think about the condition and the input values.

Since B is '0', the condition A = '1' and B = '1' is false, so Y is assigned '0'.

🧠 Conceptual

intermediate

Why combinational logic is fundamental in VHDL

Why is combinational design considered the foundation of VHDL?

A Because it only works with analog signals.

B Because it requires clock signals to operate correctly.

C Because it uses sequential statements exclusively.

D Because it models circuits without memory elements, making behavior predictable and simple to simulate.

💡 Hint

Think about what combinational logic means in hardware.

Combinational logic produces outputs based only on current inputs without memory, making it easy to model and simulate in VHDL.

🔧 Debug

advanced

Identify the error in combinational process sensitivity list

What error will occur with this VHDL process and why? process(clk) begin Y <= A and B; end process;

VHDL

process(clk)
begin
  Y <= A and B;
end process;

A No error; process works fine as is.

B Y will not update correctly because A and B are missing from the sensitivity list.

C Syntax error due to missing semicolon after Y assignment.

D Runtime error because clk is not used inside the process.

💡 Hint

Consider what signals must be in the sensitivity list for combinational logic.

For combinational processes, all input signals used must be in the sensitivity list to update outputs correctly.

📝 Syntax

advanced

Correct syntax for combinational assignment

Which option shows the correct VHDL syntax for a combinational assignment of Y as AND of A and B?

A Y <= A and B;

B Y = A and B;

C Y := A and B;

D Y == A and B;

💡 Hint

Remember the assignment operator in VHDL for signals.

In VHDL, signal assignment uses '<=' operator, not '=', ':=', or '=='.

🚀 Application

expert

Number of output changes in combinational logic

Given the following VHDL combinational process, how many times will output Y change if inputs A and B cycle through all combinations (00, 01, 10, 11) once?

VHDL

process(A, B)
begin
  Y <= A xor B;
end process;

A 2 times

B 4 times

C 3 times

D 1 time

💡 Hint

Trace output Y for each input combination change.

Y changes whenever A xor B changes. Cycling through 00(0)->01(1) change, 01(1)->10(1) no change, 10(1)->11(0) change. Total 2 changes.

Practice

1. Why is combinational design considered the foundation of VHDL?

easy

A. Because it models logic where outputs depend only on current inputs without memory

B. Because it stores data for future use

C. Because it controls the timing of signals

D. Because it handles communication between devices

Solution

1. Step 1: Understand combinational logic basics

   Combinational logic circuits produce outputs based solely on current inputs, without storing any past information.

2. Step 2: Relate to VHDL foundation

   VHDL models hardware behavior, and combinational design is the simplest form, forming the base for more complex designs.

3. Final Answer:

   Because it models logic where outputs depend only on current inputs without memory -> Option A

4. Quick Check:

   Combinational logic = output depends only on current inputs [OK]

Hint: Combinational means no memory, output depends on inputs only [OK]

Common Mistakes:

• Confusing combinational with sequential logic
• Thinking combinational stores data
• Assuming timing control is combinational's role

2. Which of the following is the correct VHDL syntax to describe a combinational process?

easy

A. process(clk) begin if rising_edge(clk) then output <= input; end if; end process;

B. process(input1, input2) begin output <= input1 and input2; end process;

C. process(reset) begin output <= '0'; end process;

D. process(clk, reset) begin if reset = '1' then output <= '0'; end if; end process;

Solution

1. Step 1: Identify combinational process sensitivity list

   Combinational processes list all inputs that affect outputs in the sensitivity list, without clock signals.

2. Step 2: Check each option

   process(input1, input2) begin output <= input1 and input2; end process; uses inputs in sensitivity list and assigns output directly, matching combinational logic style.

3. Final Answer:

   process(input1, input2) begin output <= input1 and input2; end process; -> Option B

4. Quick Check:

   Combinational process sensitivity list = inputs only [OK]

Hint: Combinational process sensitivity list has inputs, no clock [OK]

Common Mistakes:

• Including clock signals in combinational process
• Using if rising_edge in combinational logic
• Missing inputs in sensitivity list

3. Given this VHDL code snippet, what is the output when input1 = '1' and input2 = '0'?

process(input1, input2)
begin
  output <= input1 or input2;
end process;

medium

A. '0'

B. Error

C. Undefined

D. '1'

Solution

1. Step 1: Understand the logic operation

   The process assigns output as the logical OR of input1 and input2.

2. Step 2: Calculate output for given inputs

   input1 = '1', input2 = '0', so '1' OR '0' = '1'.

3. Final Answer:

   '1' -> Option D

4. Quick Check:

   1 OR 0 = 1 [OK]

Hint: OR gate outputs 1 if any input is 1 [OK]

Common Mistakes:

• Confusing OR with AND operation
• Assuming output is '0' when one input is '1'
• Thinking output is undefined without clock

4. Identify the error in this VHDL combinational process:

process(a, b)
begin
  if a = '1' then
    y <= '1';
  elsif b = '1' then
    y <= '0';
  end if;
end process;

medium

A. Missing else clause causing latch inference

B. Incorrect sensitivity list

C. Wrong signal assignment operator

D. Using clock signal in combinational process

Solution

1. Step 1: Analyze conditional branches

   The process assigns y only when a='1' or b='1', but no assignment if both are '0'.

2. Step 2: Understand latch inference

   Missing else means y keeps previous value, causing unintended latch (memory) behavior in combinational logic.

3. Final Answer:

   Missing else clause causing latch inference -> Option A

4. Quick Check:

   All paths must assign output in combinational process [OK]

Hint: Always assign outputs in all if-else branches [OK]

Common Mistakes:

• Ignoring latch inference from incomplete assignments
• Confusing sensitivity list errors with logic errors
• Thinking signal assignment operator is wrong

5. You want to design a combinational circuit in VHDL that outputs '1' only when exactly one of the three inputs a, b, or c is '1'. Which VHDL expression correctly implements this?

hard

A. output <= a or b or c;

B. output <= a and b and c;

C. output <= (a and not b and not c) or (not a and b and not c) or (not a and not b and c);

D. output <= (a and b) or (b and c) or (a and c);

Solution

1. Step 1: Understand the requirement

   Output is '1' only if exactly one input is '1', meaning one true and two false inputs.

2. Step 2: Analyze each option

   output <= (a and not b and not c) or (not a and b and not c) or (not a and not b and c); checks each input being '1' while others are '0', matching exactly one true input condition.

3. Final Answer:

   output <= (a and not b and not c) or (not a and b and not c) or (not a and not b and c); -> Option C

4. Quick Check:

   Exactly one input true = output <= (a and not b and not c) or (not a and b and not c) or (not a and not b and c); [OK]

Hint: Exactly one true means one input true, others false [OK]

Common Mistakes:

• Using OR of inputs (any true) instead of exactly one
• Using AND of inputs (all true) instead of exactly one
• Using pairs ANDed (two true) instead of one true