Why combinational design is the VHDL foundation - Performance Analysis

Time Complexity: Why combinational design is the VHDL foundation

O(n)

Understanding Time Complexity

We want to understand how the time it takes for a combinational VHDL design to run changes as the design grows.

How does adding more logic affect the time to get an output?

Scenario Under Consideration

Analyze the time complexity of the following combinational logic process.

process(a, b, c)
  begin
    y <= (a and b) or (not c);
  end process;

This code describes simple logic that combines inputs to produce an output immediately.

Identify Repeating Operations

In combinational design, there are no loops or repeated steps during execution.

• Primary operation: Logical gates (and, or, not) evaluated once per input change.
• How many times: Each gate runs once whenever inputs change, no repetition inside.

How Execution Grows With Input

As you add more logic gates, the time to get the output grows slowly because signals pass through more gates.

Input Size (n)	Approx. Operations
10 gates	10 logical operations
100 gates	100 logical operations
1000 gates	1000 logical operations

Pattern observation: The time grows roughly in a straight line with the number of gates.

Final Time Complexity

Time Complexity: O(n)

This means the time to get an output grows directly with the number of logic gates in the design.

Common Mistake

[X] Wrong: "Combinational logic runs instantly no matter how big it is."

[OK] Correct: Even though it is fast, signals still take time to pass through each gate, so bigger designs take longer.

Interview Connect

Understanding how combinational logic timing grows helps you design circuits that work reliably and efficiently.

Self-Check

"What if we added feedback loops to make the design sequential? How would the time complexity change?"