Stimulus process with wait statements in VHDL - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to wait for 10 ns before changing the signal.

VHDL

process
begin
    signal_a <= '1';
    wait for [1];
    signal_a <= '0';
    wait;
end process;

Drag options to blanks, or click blank then click option'

A10 s

B10 ns

C10 ms

D10 ps

Attempts:

3 left

💡 Hint

Common Mistakes

Using incorrect time units like seconds or milliseconds which are too large for typical signal delays.

Omitting the time unit after the number.

The wait for statement pauses the process for the specified time. Here, 10 ns is the correct time unit for typical VHDL simulation delays.

2fill in blank

medium

Complete the code to wait until the rising edge of the clock signal.

VHDL

process
begin
    wait until [1] = '1' and [1]'event;
    signal_b <= not signal_b;
end process;

Drag options to blanks, or click blank then click option'

Aclock

Breset

Cenable

Ddata

Attempts:

3 left

💡 Hint

Common Mistakes

Waiting on the wrong signal instead of the clock.

Using wait for instead of wait until for edge detection.

The wait until statement waits for a condition. To wait for the rising edge of the clock, we check when clock = '1' and clock'event is true.

3fill in blank

hard

Fix the error in the wait statement to correctly wait for 20 ns.

VHDL

process
begin
    signal_c <= '1';
    wait for [1];
    signal_c <= '0';
    wait;
end process;

Drag options to blanks, or click blank then click option'

A20 ns

B20

C'20 ns'

D20ns

Attempts:

3 left

💡 Hint

Common Mistakes

Writing the time value as a string with quotes.

Omitting the space between number and unit.

The wait for statement requires a number followed by a space and a time unit without quotes. So wait for 20 ns; is correct.

4fill in blank

hard

Fill both blanks to create a process that waits for 5 ns, sets signal_d to '1', then waits for 10 ns.

VHDL

process
begin
    wait for [1];
    signal_d <= '1';
    wait for [2];
    signal_d <= '0';
    wait;
end process;

Drag options to blanks, or click blank then click option'

A5 ns

B10 ns

C15 ns

D20 ns

Attempts:

3 left

💡 Hint

Common Mistakes

Swapping the wait times.

Using incorrect time units.

The process first waits 5 ns, sets the signal, then waits 10 ns before resetting it. So the blanks are filled with 5 ns and 10 ns.

5fill in blank

hard

Fill all three blanks to create a process that waits for a rising edge of clk, sets signal_e to '1', then waits for 15 ns.

VHDL

process
begin
    wait until [1] = '1' and [2]'event;
    signal_e <= '1';
    wait for [3];
    signal_e <= '0';
    wait;
end process;

Drag options to blanks, or click blank then click option'

Aclk

Bclock

C15 ns

Dclk_signal

Attempts:

3 left

💡 Hint

Common Mistakes

Using different signals for the clock in the wait until condition.

Incorrect time unit or missing space in the wait for statement.

The process waits for the rising edge of clk (so both blanks are clk), then waits for 15 ns before resetting the signal.