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VHDLprogramming~10 mins

Stimulus process with wait statements in VHDL - Interactive Code Practice

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Practice - 5 Tasks
Answer the questions below
1fill in blank
easy

Complete the code to wait for 10 ns before changing the signal.

VHDL
process
begin
    signal_a <= '1';
    wait for [1];
    signal_a <= '0';
    wait;
end process;
Drag options to blanks, or click blank then click option'
A10 s
B10 ns
C10 ms
D10 ps
Attempts:
3 left
💡 Hint
Common Mistakes
Using incorrect time units like seconds or milliseconds which are too large for typical signal delays.
Omitting the time unit after the number.
2fill in blank
medium

Complete the code to wait until the rising edge of the clock signal.

VHDL
process
begin
    wait until [1] = '1' and [1]'event;
    signal_b <= not signal_b;
end process;
Drag options to blanks, or click blank then click option'
Aclock
Breset
Cenable
Ddata
Attempts:
3 left
💡 Hint
Common Mistakes
Waiting on the wrong signal instead of the clock.
Using wait for instead of wait until for edge detection.
3fill in blank
hard

Fix the error in the wait statement to correctly wait for 20 ns.

VHDL
process
begin
    signal_c <= '1';
    wait for [1];
    signal_c <= '0';
    wait;
end process;
Drag options to blanks, or click blank then click option'
A20 ns
B20
C'20 ns'
D20ns
Attempts:
3 left
💡 Hint
Common Mistakes
Writing the time value as a string with quotes.
Omitting the space between number and unit.
4fill in blank
hard

Fill both blanks to create a process that waits for 5 ns, sets signal_d to '1', then waits for 10 ns.

VHDL
process
begin
    wait for [1];
    signal_d <= '1';
    wait for [2];
    signal_d <= '0';
    wait;
end process;
Drag options to blanks, or click blank then click option'
A5 ns
B10 ns
C15 ns
D20 ns
Attempts:
3 left
💡 Hint
Common Mistakes
Swapping the wait times.
Using incorrect time units.
5fill in blank
hard

Fill all three blanks to create a process that waits for a rising edge of clk, sets signal_e to '1', then waits for 15 ns.

VHDL
process
begin
    wait until [1] = '1' and [2]'event;
    signal_e <= '1';
    wait for [3];
    signal_e <= '0';
    wait;
end process;
Drag options to blanks, or click blank then click option'
Aclk
Bclock
C15 ns
Dclk_signal
Attempts:
3 left
💡 Hint
Common Mistakes
Using different signals for the clock in the wait until condition.
Incorrect time unit or missing space in the wait for statement.

Practice

(1/5)
1. What is the main purpose of using wait for statements inside a stimulus process in VHDL?
easy
A. To declare variables inside the process
B. To pause the process and apply inputs step-by-step over time
C. To define the clock period for the design
D. To reset all signals to zero immediately

Solution

  1. Step 1: Understand the role of stimulus processes

    Stimulus processes apply test inputs to signals during simulation.
  2. Step 2: Identify the function of wait for

    The wait for statement pauses the process for a specified time, allowing signals to hold values before changing again.
  3. Final Answer:

    To pause the process and apply inputs step-by-step over time -> Option B
  4. Quick Check:

    Stimulus process uses wait for to pause and apply inputs [OK]
Hint: Wait statements pause input changes to simulate time steps [OK]
Common Mistakes:
  • Thinking wait for resets signals
  • Confusing wait for with variable declaration
  • Assuming wait for defines clock period
2. Which of the following is the correct way to end a stimulus process in VHDL to stop it from running indefinitely?
easy
A. wait;
B. stop;
C. end process;
D. wait for 10 ns;

Solution

  1. Step 1: Review how stimulus processes terminate

    Stimulus processes often run indefinitely unless explicitly stopped.
  2. Step 2: Identify the correct wait statement to stop the process

    The statement wait; causes the process to suspend forever, effectively stopping it.
  3. Final Answer:

    wait; -> Option A
  4. Quick Check:

    Use wait; to stop stimulus process [OK]
Hint: Use plain wait; to stop stimulus process execution [OK]
Common Mistakes:
  • Using wait for with a time instead of wait;
  • Trying to use end process; as a stop command
  • Using stop; which is not valid VHDL
3. Consider the following VHDL stimulus process snippet:
process
  begin
    signal_a <= '0';
    wait for 10 ns;
    signal_a <= '1';
    wait for 20 ns;
    wait;
end process;
What is the value of signal_a at 25 ns after simulation start?
medium
A. '0'
B. Undefined
C. '1'
D. Signal does not change

Solution

  1. Step 1: Trace signal assignments over time

    At 0 ns, signal_a is set to '0'. After 10 ns, it changes to '1'.
  2. Step 2: Determine signal value at 25 ns

    At 25 ns, which is after the 10 ns and before the 30 ns (10+20), signal_a remains '1'.
  3. Final Answer:

    '1' -> Option C
  4. Quick Check:

    Signal changes at 10 ns to '1', stays until 30 ns [OK]
Hint: Add wait times cumulatively to find signal value at given time [OK]
Common Mistakes:
  • Assuming signal_a is still '0' at 25 ns
  • Ignoring the second wait for 20 ns
  • Confusing wait; with wait for
4. Identify the error in the following stimulus process code:
process
begin
  signal_b <= '1';
  wait for 5 ns
  signal_b <= '0';
  wait for 5 ns;
  wait;
end process;
medium
A. Missing semicolon after first wait for statement
B. Signal assignment syntax is incorrect
C. wait; statement is misplaced
D. Process missing sensitivity list

Solution

  1. Step 1: Check syntax of wait statements

    The first wait for 5 ns is missing a semicolon at the end.
  2. Step 2: Confirm other syntax elements

    Signal assignments and the final wait; are correct. Sensitivity list is not required in a process with wait statements.
  3. Final Answer:

    Missing semicolon after first wait for statement -> Option A
  4. Quick Check:

    Every wait for must end with semicolon [OK]
Hint: Check semicolons after wait for statements carefully [OK]
Common Mistakes:
  • Thinking sensitivity list is required with wait
  • Misreading signal assignment syntax
  • Assuming wait; must be last line only
5. You want to create a stimulus process that toggles clk every 15 ns and stops after 90 ns. Which code snippet correctly implements this behavior?
hard
A. process begin clk <= '0'; wait for 15 ns; clk <= '1'; wait for 15 ns; wait; end process;
B. process begin clk <= '0'; wait for 90 ns; clk <= '1'; wait; end process;
C. process begin for i in 0 to 5 loop clk <= '0'; wait for 15 ns; clk <= '1'; wait for 15 ns; end loop; wait; end process;
D. process variable count : integer := 0; begin while count < 6 loop clk <= not clk; wait for 15 ns; count := count + 1; end loop; wait; end process;

Solution

  1. Step 1: Understand toggling every 15 ns for 90 ns

    Toggling means changing clk from 0 to 1 or 1 to 0 every 15 ns. For 90 ns total, toggling happens 6 times (90/15).
  2. Step 2: Analyze each option's logic

    process variable count : integer := 0; begin while count < 6 loop clk <= not clk; wait for 15 ns; count := count + 1; end loop; wait; end process; uses a loop with a counter to toggle clk 6 times, waiting 15 ns each time, then stops with wait;. Others either toggle once or use incorrect timing.
  3. Final Answer:

    variable count : integer := 0; while count < 6 loop clk <= not clk; wait for 15 ns; count := count + 1; end loop; wait; -> Option D
  4. Quick Check:

    Loop with wait for 15 ns toggles clk 6 times [OK]
Hint: Use loop with counter and wait for to toggle signals repeatedly [OK]
Common Mistakes:
  • Using single wait for without loop for repeated toggling
  • Incorrect loop ranges causing wrong toggle count
  • Not stopping process after toggling
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