Stimulus process with wait statements in VHDL - Mini Project: Build & Apply

Stimulus Process with Wait Statements in VHDL

📖 Scenario: You are designing a simple testbench for a digital circuit. You want to create a stimulus process that applies different input values to your circuit at specific time intervals using wait statements.

🎯 Goal: Build a VHDL stimulus process that changes an input signal input_signal at different times using wait for statements to control timing.

📋 What You'll Learn

Create a signal input_signal of type std_logic initialized to '0'.

Add a stimulus process named stim_proc.

Inside the process, assign input_signal to '1', then wait for 10 ns.

Then assign input_signal to '0', then wait for 20 ns.

Finally, assign input_signal to '1' again.

💡 Why This Matters

🌍 Real World

Stimulus processes with wait statements are used in testbenches to simulate input signals changing over time, helping verify digital circuit behavior before hardware implementation.

💼 Career

Understanding stimulus processes and timing control is essential for hardware engineers and FPGA developers to create effective testbenches and ensure correct circuit operation.

1

Create the input signal

Create a signal called input_signal of type std_logic and initialize it to '0'.

VHDL

-- Your code here

Hint

Use the syntax signal name : type := initial_value; to declare a signal.

2

Add the stimulus process

Add a process named stim_proc with no sensitivity list.

VHDL

signal input_signal : std_logic := '0';

-- Your code here

Hint

Use process keyword without sensitivity list and name it stim_proc.

3

Apply input changes with wait statements

Inside the stim_proc process, assign input_signal to '1', then wait for 10 ns;. Next, assign input_signal to '0', then wait for 20 ns;. Finally, assign input_signal to '1'.

VHDL

signal input_signal : std_logic := '0';

stim_proc: process
begin
    -- Your code here
end process stim_proc;

Hint

Use input_signal <= 'value'; to assign values and wait for time; to pause.

4

Print the input signal changes (simulation output)

Add report statements after each assignment inside stim_proc to print the current value of input_signal as a string.

VHDL

signal input_signal : std_logic := '0';

stim_proc: process
begin
    -- Your code here
end process stim_proc;

Hint

Use report "message"; to print messages during simulation.

Practice

1. What is the main purpose of using wait for statements inside a stimulus process in VHDL?

easy

A. To declare variables inside the process

B. To pause the process and apply inputs step-by-step over time

C. To define the clock period for the design

D. To reset all signals to zero immediately

Solution

1. Step 1: Understand the role of stimulus processes

   Stimulus processes apply test inputs to signals during simulation.

2. Step 2: Identify the function of wait for

   The wait for statement pauses the process for a specified time, allowing signals to hold values before changing again.

3. Final Answer:

   To pause the process and apply inputs step-by-step over time -> Option B

4. Quick Check:

   Stimulus process uses wait for to pause and apply inputs [OK]

Hint: Wait statements pause input changes to simulate time steps [OK]

Common Mistakes:

• Thinking wait for resets signals
• Confusing wait for with variable declaration
• Assuming wait for defines clock period

2. Which of the following is the correct way to end a stimulus process in VHDL to stop it from running indefinitely?

easy

A. wait;

B. stop;

C. end process;

D. wait for 10 ns;

Solution

1. Step 1: Review how stimulus processes terminate

   Stimulus processes often run indefinitely unless explicitly stopped.

2. Step 2: Identify the correct wait statement to stop the process

   The statement wait; causes the process to suspend forever, effectively stopping it.

3. Final Answer:

   wait; -> Option A

4. Quick Check:

   Use wait; to stop stimulus process [OK]

Hint: Use plain wait; to stop stimulus process execution [OK]

Common Mistakes:

• Using wait for with a time instead of wait;
• Trying to use end process; as a stop command
• Using stop; which is not valid VHDL

3. Consider the following VHDL stimulus process snippet:

process
  begin
    signal_a <= '0';
    wait for 10 ns;
    signal_a <= '1';
    wait for 20 ns;
    wait;
end process;

What is the value of signal_a at 25 ns after simulation start?

medium

A. '0'

B. Undefined

C. '1'

D. Signal does not change

Solution

1. Step 1: Trace signal assignments over time

   At 0 ns, signal_a is set to '0'. After 10 ns, it changes to '1'.

2. Step 2: Determine signal value at 25 ns

   At 25 ns, which is after the 10 ns and before the 30 ns (10+20), signal_a remains '1'.

3. Final Answer:

   '1' -> Option C

4. Quick Check:

   Signal changes at 10 ns to '1', stays until 30 ns [OK]

Hint: Add wait times cumulatively to find signal value at given time [OK]

Common Mistakes:

• Assuming signal_a is still '0' at 25 ns
• Ignoring the second wait for 20 ns
• Confusing wait; with wait for

4. Identify the error in the following stimulus process code:

process
begin
  signal_b <= '1';
  wait for 5 ns
  signal_b <= '0';
  wait for 5 ns;
  wait;
end process;

medium

A. Missing semicolon after first wait for statement

B. Signal assignment syntax is incorrect

C. wait; statement is misplaced

D. Process missing sensitivity list

Solution

1. Step 1: Check syntax of wait statements

   The first wait for 5 ns is missing a semicolon at the end.

2. Step 2: Confirm other syntax elements

   Signal assignments and the final wait; are correct. Sensitivity list is not required in a process with wait statements.

3. Final Answer:

   Missing semicolon after first wait for statement -> Option A

4. Quick Check:

   Every wait for must end with semicolon [OK]

Hint: Check semicolons after wait for statements carefully [OK]

Common Mistakes:

• Thinking sensitivity list is required with wait
• Misreading signal assignment syntax
• Assuming wait; must be last line only

5. You want to create a stimulus process that toggles clk every 15 ns and stops after 90 ns. Which code snippet correctly implements this behavior?

hard

A. process
begin
clk <= '0';
wait for 15 ns;
clk <= '1';
wait for 15 ns;
wait;
end process;

B. process
begin
clk <= '0';
wait for 90 ns;
clk <= '1';
wait;
end process;

C. process
begin
for i in 0 to 5 loop
clk <= '0';
wait for 15 ns;
clk <= '1';
wait for 15 ns;
end loop;
wait;
end process;

D. process
variable count : integer := 0;
begin
while count < 6 loop
clk <= not clk;
wait for 15 ns;
count := count + 1;
end loop;
wait;
end process;

Solution

1. Step 1: Understand toggling every 15 ns for 90 ns

   Toggling means changing clk from 0 to 1 or 1 to 0 every 15 ns. For 90 ns total, toggling happens 6 times (90/15).

2. Step 2: Analyze each option's logic

   process variable count : integer := 0; begin while count < 6 loop clk <= not clk; wait for 15 ns; count := count + 1; end loop; wait; end process; uses a loop with a counter to toggle clk 6 times, waiting 15 ns each time, then stops with wait;. Others either toggle once or use incorrect timing.

3. Final Answer:

   variable count : integer := 0; while count < 6 loop clk <= not clk; wait for 15 ns; count := count + 1; end loop; wait; -> Option D

4. Quick Check:

   Loop with wait for 15 ns toggles clk 6 times [OK]

Hint: Use loop with counter and wait for to toggle signals repeatedly [OK]

Common Mistakes:

• Using single wait for without loop for repeated toggling
• Incorrect loop ranges causing wrong toggle count
• Not stopping process after toggling