Stimulus process with wait statements in VHDL - Mini Project: Build & Apply

Stimulus Process with Wait Statements in VHDL

📖 Scenario: You are designing a simple testbench for a digital circuit. You want to create a stimulus process that applies different input values to your circuit at specific time intervals using wait statements.

🎯 Goal: Build a VHDL stimulus process that changes an input signal input_signal at different times using wait for statements to control timing.

📋 What You'll Learn

Create a signal input_signal of type std_logic initialized to '0'.

Add a stimulus process named stim_proc.

Inside the process, assign input_signal to '1', then wait for 10 ns.

Then assign input_signal to '0', then wait for 20 ns.

Finally, assign input_signal to '1' again.

💡 Why This Matters

🌍 Real World

Stimulus processes with wait statements are used in testbenches to simulate input signals changing over time, helping verify digital circuit behavior before hardware implementation.

💼 Career

Understanding stimulus processes and timing control is essential for hardware engineers and FPGA developers to create effective testbenches and ensure correct circuit operation.

1

Create the input signal

Create a signal called input_signal of type std_logic and initialize it to '0'.

VHDL

-- Your code here

Need a hint?

Use the syntax signal name : type := initial_value; to declare a signal.

2

Add the stimulus process

Add a process named stim_proc with no sensitivity list.

VHDL

signal input_signal : std_logic := '0';

-- Your code here

Need a hint?

Use process keyword without sensitivity list and name it stim_proc.

3

Apply input changes with wait statements

Inside the stim_proc process, assign input_signal to '1', then wait for 10 ns;. Next, assign input_signal to '0', then wait for 20 ns;. Finally, assign input_signal to '1'.

VHDL

signal input_signal : std_logic := '0';

stim_proc: process
begin
    -- Your code here
end process stim_proc;

Need a hint?

Use input_signal <= 'value'; to assign values and wait for time; to pause.

4

Print the input signal changes (simulation output)

Add report statements after each assignment inside stim_proc to print the current value of input_signal as a string.

VHDL

signal input_signal : std_logic := '0';

stim_proc: process
begin
    -- Your code here
end process stim_proc;

Need a hint?

Use report "message"; to print messages during simulation.