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VHDLprogramming~20 mins

Stimulus process with wait statements in VHDL - Practice Problems & Coding Challenges

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Challenge - 5 Problems
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Stimulus Process Mastery
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❓ Predict Output
intermediate
2:00remaining
Output of a stimulus process with sequential wait statements

Consider the following VHDL stimulus process. What will be the value of signal_a after 30 ns?

VHDL
process
begin
  signal_a <= '0';
  wait for 10 ns;
  signal_a <= '1';
  wait for 10 ns;
  signal_a <= '0';
  wait for 10 ns;
  wait;
end process;
ASignal retains previous value before process
B'1'
CUndefined (signal_a is not assigned)
D'0'
Attempts:
2 left
💡 Hint

Think about how the signal changes at each wait statement and the total elapsed time.

❓ Predict Output
intermediate
2:00remaining
Value of signal after multiple wait statements with different durations

Given this VHDL stimulus process, what is the value of signal_b at 25 ns?

VHDL
process
begin
  signal_b <= '1';
  wait for 5 ns;
  signal_b <= '0';
  wait for 15 ns;
  signal_b <= '1';
  wait for 10 ns;
  wait;
end process;
A'1'
B'0'
C'U' (undefined)
DSignal retains initial value
Attempts:
2 left
💡 Hint

Calculate the time intervals and see which assignment is active at 25 ns.

❓ Predict Output
advanced
2:00remaining
Output of a stimulus process with wait until and wait for combined

What will be the value of signal_c at 50 ns given this process?

VHDL
process
begin
  signal_c <= '0';
  wait until now = 20 ns;
  signal_c <= '1';
  wait for 20 ns;
  signal_c <= '0';
  wait;
end process;
A'0'
B'1'
CProcess will hang and signal_c remains '0'
DSignal_c is 'U' (undefined)
Attempts:
2 left
💡 Hint

Consider how wait until and wait for affect the timing of assignments.

❓ Predict Output
advanced
2:00remaining
Effect of multiple wait statements on process execution

What is the final value of signal_d after this process completes?

VHDL
process
begin
  signal_d <= '1';
  wait for 10 ns;
  signal_d <= '0';
  wait for 10 ns;
  signal_d <= '1';
  wait for 10 ns;
  signal_d <= '0';
  wait;
end process;
AProcess never completes, signal_d remains '1'
B'1'
C'0'
DSignal_d is 'U' (undefined)
Attempts:
2 left
💡 Hint

Follow the signal assignments and wait times step by step.

🧠 Conceptual
expert
2:00remaining
Understanding process suspension with wait statements

In a VHDL stimulus process with multiple wait statements, what happens to the process execution after the last wait; statement?

AThe process restarts from the beginning immediately
BThe process suspends indefinitely and does not resume unless triggered externally
CThe process terminates and cannot be resumed
DThe process continues executing the next statements sequentially
Attempts:
2 left
💡 Hint

Think about how wait; without conditions affects process behavior.

Practice

(1/5)
1. What is the main purpose of using wait for statements inside a stimulus process in VHDL?
easy
A. To declare variables inside the process
B. To pause the process and apply inputs step-by-step over time
C. To define the clock period for the design
D. To reset all signals to zero immediately

Solution

  1. Step 1: Understand the role of stimulus processes

    Stimulus processes apply test inputs to signals during simulation.
  2. Step 2: Identify the function of wait for

    The wait for statement pauses the process for a specified time, allowing signals to hold values before changing again.
  3. Final Answer:

    To pause the process and apply inputs step-by-step over time -> Option B
  4. Quick Check:

    Stimulus process uses wait for to pause and apply inputs [OK]
Hint: Wait statements pause input changes to simulate time steps [OK]
Common Mistakes:
  • Thinking wait for resets signals
  • Confusing wait for with variable declaration
  • Assuming wait for defines clock period
2. Which of the following is the correct way to end a stimulus process in VHDL to stop it from running indefinitely?
easy
A. wait;
B. stop;
C. end process;
D. wait for 10 ns;

Solution

  1. Step 1: Review how stimulus processes terminate

    Stimulus processes often run indefinitely unless explicitly stopped.
  2. Step 2: Identify the correct wait statement to stop the process

    The statement wait; causes the process to suspend forever, effectively stopping it.
  3. Final Answer:

    wait; -> Option A
  4. Quick Check:

    Use wait; to stop stimulus process [OK]
Hint: Use plain wait; to stop stimulus process execution [OK]
Common Mistakes:
  • Using wait for with a time instead of wait;
  • Trying to use end process; as a stop command
  • Using stop; which is not valid VHDL
3. Consider the following VHDL stimulus process snippet:
process
  begin
    signal_a <= '0';
    wait for 10 ns;
    signal_a <= '1';
    wait for 20 ns;
    wait;
end process;
What is the value of signal_a at 25 ns after simulation start?
medium
A. '0'
B. Undefined
C. '1'
D. Signal does not change

Solution

  1. Step 1: Trace signal assignments over time

    At 0 ns, signal_a is set to '0'. After 10 ns, it changes to '1'.
  2. Step 2: Determine signal value at 25 ns

    At 25 ns, which is after the 10 ns and before the 30 ns (10+20), signal_a remains '1'.
  3. Final Answer:

    '1' -> Option C
  4. Quick Check:

    Signal changes at 10 ns to '1', stays until 30 ns [OK]
Hint: Add wait times cumulatively to find signal value at given time [OK]
Common Mistakes:
  • Assuming signal_a is still '0' at 25 ns
  • Ignoring the second wait for 20 ns
  • Confusing wait; with wait for
4. Identify the error in the following stimulus process code:
process
begin
  signal_b <= '1';
  wait for 5 ns
  signal_b <= '0';
  wait for 5 ns;
  wait;
end process;
medium
A. Missing semicolon after first wait for statement
B. Signal assignment syntax is incorrect
C. wait; statement is misplaced
D. Process missing sensitivity list

Solution

  1. Step 1: Check syntax of wait statements

    The first wait for 5 ns is missing a semicolon at the end.
  2. Step 2: Confirm other syntax elements

    Signal assignments and the final wait; are correct. Sensitivity list is not required in a process with wait statements.
  3. Final Answer:

    Missing semicolon after first wait for statement -> Option A
  4. Quick Check:

    Every wait for must end with semicolon [OK]
Hint: Check semicolons after wait for statements carefully [OK]
Common Mistakes:
  • Thinking sensitivity list is required with wait
  • Misreading signal assignment syntax
  • Assuming wait; must be last line only
5. You want to create a stimulus process that toggles clk every 15 ns and stops after 90 ns. Which code snippet correctly implements this behavior?
hard
A. process begin clk <= '0'; wait for 15 ns; clk <= '1'; wait for 15 ns; wait; end process;
B. process begin clk <= '0'; wait for 90 ns; clk <= '1'; wait; end process;
C. process begin for i in 0 to 5 loop clk <= '0'; wait for 15 ns; clk <= '1'; wait for 15 ns; end loop; wait; end process;
D. process variable count : integer := 0; begin while count < 6 loop clk <= not clk; wait for 15 ns; count := count + 1; end loop; wait; end process;

Solution

  1. Step 1: Understand toggling every 15 ns for 90 ns

    Toggling means changing clk from 0 to 1 or 1 to 0 every 15 ns. For 90 ns total, toggling happens 6 times (90/15).
  2. Step 2: Analyze each option's logic

    process variable count : integer := 0; begin while count < 6 loop clk <= not clk; wait for 15 ns; count := count + 1; end loop; wait; end process; uses a loop with a counter to toggle clk 6 times, waiting 15 ns each time, then stops with wait;. Others either toggle once or use incorrect timing.
  3. Final Answer:

    variable count : integer := 0; while count < 6 loop clk <= not clk; wait for 15 ns; count := count + 1; end loop; wait; -> Option D
  4. Quick Check:

    Loop with wait for 15 ns toggles clk 6 times [OK]
Hint: Use loop with counter and wait for to toggle signals repeatedly [OK]
Common Mistakes:
  • Using single wait for without loop for repeated toggling
  • Incorrect loop ranges causing wrong toggle count
  • Not stopping process after toggling
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