Stimulus process with wait statements in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of a stimulus process with sequential wait statements

Consider the following VHDL stimulus process. What will be the value of signal_a after 30 ns?

VHDL

process
begin
  signal_a <= '0';
  wait for 10 ns;
  signal_a <= '1';
  wait for 10 ns;
  signal_a <= '0';
  wait for 10 ns;
  wait;
end process;

A Signal retains previous value before process

B '1'

C Undefined (signal_a is not assigned)

D '0'

💡 Hint

Think about how the signal changes at each wait statement and the total elapsed time.

The process assigns '0' at 0 ns, then waits 10 ns. At 10 ns, it assigns '1', then waits 10 ns. At 20 ns, it assigns '0' again, then waits 10 ns. At 30 ns, the last assignment was '0'.

❓ Predict Output

intermediate

Value of signal after multiple wait statements with different durations

Given this VHDL stimulus process, what is the value of signal_b at 25 ns?

VHDL

process
begin
  signal_b <= '1';
  wait for 5 ns;
  signal_b <= '0';
  wait for 15 ns;
  signal_b <= '1';
  wait for 10 ns;
  wait;
end process;

A '1'

B '0'

C 'U' (undefined)

D Signal retains initial value

💡 Hint

Calculate the time intervals and see which assignment is active at 25 ns.

At 0 ns, signal_b = '1'. After 5 ns, it changes to '0'. After 20 ns (5+15), it changes to '1'. At 25 ns, which is between 20 ns and 30 ns, signal_b is '1'. But wait, 25 ns is after 20 ns assignment to '1'. So the correct value is '1'.

❓ Predict Output

advanced

Output of a stimulus process with wait until and wait for combined

What will be the value of signal_c at 50 ns given this process?

VHDL

process
begin
  signal_c <= '0';
  wait until now = 20 ns;
  signal_c <= '1';
  wait for 20 ns;
  signal_c <= '0';
  wait;
end process;

A '0'

B '1'

C Process will hang and signal_c remains '0'

D Signal_c is 'U' (undefined)

💡 Hint

Consider how wait until and wait for affect the timing of assignments.

The process waits until 20 ns, then assigns '1'. Then it waits 20 ns more (until 40 ns), assigns '0'. At 50 ns, the last assignment was '0'.

❓ Predict Output

advanced

Effect of multiple wait statements on process execution

What is the final value of signal_d after this process completes?

VHDL

process
begin
  signal_d <= '1';
  wait for 10 ns;
  signal_d <= '0';
  wait for 10 ns;
  signal_d <= '1';
  wait for 10 ns;
  signal_d <= '0';
  wait;
end process;

A Process never completes, signal_d remains '1'

B '1'

C '0'

D Signal_d is 'U' (undefined)

💡 Hint

Follow the signal assignments and wait times step by step.

The signal changes at 0 ns to '1', at 10 ns to '0', at 20 ns to '1', and at 30 ns to '0'. The process then waits indefinitely. So the final value is '0'.

🧠 Conceptual

expert

Understanding process suspension with wait statements

In a VHDL stimulus process with multiple wait statements, what happens to the process execution after the last wait; statement?

A The process restarts from the beginning immediately

B The process suspends indefinitely and does not resume unless triggered externally

C The process terminates and cannot be resumed

D The process continues executing the next statements sequentially

💡 Hint

Think about how wait; without conditions affects process behavior.

A wait; statement without any condition causes the process to suspend indefinitely. It will only resume if an external event triggers it (like a signal change if sensitivity list or wait conditions exist). It does not restart or terminate.