Signal vs variable vs constant in VHDL - Visual Side-by-Side Comparison

Concept Flow - Signal vs variable vs constant

Start Process

↓

Declare constant

↓

Declare variable

↓

Declare signal

↓

Assign values

↓

Evaluate variable immediately

↓

Update signal at process end

↓

Use constant value anytime

↓

End Process

This flow shows how constants, variables, and signals are declared and updated inside a VHDL process, highlighting when their values change.

Execution Sample

VHDL

process
  constant C : integer := 5;
  variable V : integer := 0;
  signal S : integer := 0;
begin
  V := C + 1;
  S <= V + 1;
end process;

This VHDL process declares a constant, a variable, and a signal, then assigns values to variable and signal based on the constant and variable.

Execution Table

Step	Action	Constant C	Variable V	Signal S	Notes
1	Start process	5	0	0	Constant C initialized to 5, Variable V initialized to 0, Signal S initial value 0
2	Assign V := C + 1	5	6	0	Variable V updated immediately to 6
3	Assign S <= V + 1	5	6	0	Signal S scheduled to update to 7 at process end
4	End process - Signal update	5	6	7	Signal S updated to 7 after process completes

💡 Process ends, signal S updates after process, variable V updated immediately, constant C unchanged

Variable Tracker

Variable	Start	After Step 2	After Step 3	After Step 4 (final)
C (constant)	5	5	5	5
V (variable)	0	6	6	6
S (signal)	0	0	0	7

Key Moments - 3 Insights

Why does the variable V change immediately but the signal S does not?

Variables update instantly within the process (see Step 2), but signals schedule their update to happen only after the process ends (see Step 4). This means signal S keeps its old value during the process.

Can the constant C be changed during the process?

No, constants keep their value fixed throughout the process (see all steps in execution_table where C remains 5). You cannot assign a new value to a constant.

Why is the signal S value still 0 after assigning S <= V + 1 in Step 3?

Signal assignments inside a process do not take effect immediately; they are scheduled and updated only after the process finishes (see Step 4). So S remains 0 during the process.

Visual Quiz - 3 Questions

Look at the execution table, what is the value of variable V immediately after Step 2?

A 0

B 5

C 6

D undefined

💡 Hint

Check the 'Variable V' column at Step 2 in the execution_table.

At which step does the signal S actually update to its new value?

A Step 2

B Step 4

C Step 3

D Signal never updates

💡 Hint

Look at the 'Signal S' column in execution_table and see when it changes from 0 to 7.

If we tried to assign a new value to constant C inside the process, what would happen?

A Compilation error because constants cannot be changed

B C would update immediately like a variable

C C would update after the process like a signal

D C would keep old value but show a warning

💡 Hint

Refer to key_moments about constant behavior and immutability.

Concept Snapshot

VHDL constants hold fixed values and cannot change.
Variables update immediately inside a process.
Signals update only after the process ends.
Use constants for fixed values, variables for temporary immediate changes,
and signals for communication between processes.

Full Transcript

In VHDL, constants, variables, and signals behave differently inside a process. Constants are fixed and cannot be changed once declared. Variables update their values immediately when assigned inside the process. Signals, however, schedule their updates and only change after the process finishes. This means if you assign a new value to a signal inside a process, the old value remains during the process execution and the new value appears only after the process ends. This distinction is important for designing hardware behavior correctly. The example process shows a constant C set to 5, a variable V assigned C plus 1 immediately, and a signal S assigned V plus 1 but updated only after the process ends. Understanding these timing differences helps avoid bugs and design errors in VHDL code.

Practice

1. Which of the following best describes a signal in VHDL?

easy

A. It communicates between processes and updates after the process ends.

B. It holds a fixed value that never changes.

C. It is temporary and updates immediately inside a process.

D. It is used only for constants and cannot change.

Solution

1. Step 1: Understand the role of signals

   Signals are used to communicate between different processes in VHDL and their values update only after the process finishes executing.

2. Step 2: Compare with variables and constants

   Variables update immediately inside a process, and constants never change. Signals differ by updating after the process ends.

3. Final Answer:

   It communicates between processes and updates after the process ends. -> Option A

4. Quick Check:

   Signal = Communicates between processes [OK]

Hint: Signals update after process ends, variables update immediately [OK]

Common Mistakes:

• Confusing signals with variables updating immediately
• Thinking constants can change
• Assuming signals update instantly inside processes

2. Which of the following is the correct way to declare a constant in VHDL?

easy

A. variable MAX_VALUE : integer := 100;

B. signal MAX_VALUE : integer := 100;

C. const MAX_VALUE : integer := 100;

D. constant MAX_VALUE : integer := 100;

Solution

1. Step 1: Recall constant declaration syntax

   In VHDL, constants are declared using the keyword constant followed by the name, type, and value.

2. Step 2: Check each option

   constant MAX_VALUE : integer := 100; (D) uses constant correctly. A uses variable, B uses signal, and C uses an invalid keyword const.

3. Final Answer:

   constant MAX_VALUE : integer := 100; -> Option D

4. Quick Check:

   Constant declaration uses keyword 'constant' [OK]

Hint: Constants use keyword 'constant' not 'variable' or 'signal' [OK]

Common Mistakes:

• Using 'variable' or 'signal' instead of 'constant'
• Using 'const' which is not valid in VHDL
• Omitting the type or value in declaration

3. Consider the following VHDL process:

process
  variable temp : integer := 0;
  begin
    temp := temp + 1;
    output_signal <= temp;
end process;

What will be the value assigned to output_signal after the first process execution?

medium

A. 0

B. 1

C. Undefined

D. Error

Solution

1. Step 1: Understand variable and signal update timing

   The variable temp is initialized to 0 and updates immediately inside the process: temp := temp + 1; sets it to 1.

2. Step 2: Determine signal value after process

   The assignment output_signal <= temp; (temp=1) schedules the update to 1, which takes effect after the process ends. Thus, after the first execution, output_signal is 1.

3. Final Answer:

   1 -> Option B

4. Quick Check:

   Variable immediate, signal after process; output_signal = 1 [OK]

Hint: Signals update after process ends; variables update immediately [OK]

Common Mistakes:

• Thinking signal assignment schedules the old variable value (0)
• Confusing variable and signal update timing
• Expecting output_signal to remain 0 after process

4. Identify the error in the following VHDL code snippet:

process
  variable count : integer := 0;
begin
  count := count + 1;
  signal_flag <= count;
end process;

medium

A. No error; the code is correct.

B. Signals cannot be assigned inside a process.

C. Variables cannot be initialized inside a process.

D. Signal assignment uses '<=' but variable assignment uses ':='; mixing them is incorrect.

Solution

1. Step 1: Check variable declaration

   Variables can be declared and initialized in the process declarative region before begin, so C is wrong.

2. Step 2: Check assignment syntax

   Variables use :=, signals use <=; the code uses both correctly, so A (claiming mixing incorrect) is wrong.

3. Step 3: Check signal usage

   Signals must be assigned inside processes to drive them, so B is wrong.

4. Final Answer:

   No error; the code is correct. -> Option A

5. Quick Check:

   Correct syntax: decl before begin, proper operators [OK]

Hint: Remember '<=' for signals, ':=' for variables [OK]

Common Mistakes:

• Thinking variables can't be initialized inside processes
• Confusing signal and variable assignment operators
• Thinking mixing assignment operators is an error

5. You want to create a VHDL process that counts clock cycles and holds a fixed maximum count value. Which combination correctly uses signal, variable, and constant?

hard

A. Declare a signal MAX_COUNT, a constant count inside the process, and a variable output_count.

B. Declare a variable MAX_COUNT, a signal count inside the process, and a constant output_count.

C. Declare a constant MAX_COUNT, a variable count inside the process, and a signal output_count to communicate outside.

D. Declare all as variables inside the process.

Solution

1. Step 1: Understand roles of constant, variable, and signal

   The maximum count value should never change, so it must be a constant. The count that changes during process execution is best as a variable for immediate updates. The output count that communicates outside the process should be a signal.

2. Step 2: Match roles to options

   Declare a constant MAX_COUNT, a variable count inside the process, and a signal output_count to communicate outside. correctly assigns MAX_COUNT as constant, count as variable inside the process, and output_count as signal. Other options misuse these roles.

3. Final Answer:

   Declare a constant MAX_COUNT, a variable count inside the process, and a signal output_count to communicate outside. -> Option C

4. Quick Check:

   Constant fixed, variable immediate, signal communicates [OK]

Hint: Constant fixed, variable immediate, signal communicates outside [OK]

Common Mistakes:

• Using variable for fixed max count
• Using signal inside process for immediate updates
• Declaring all as variables ignoring constants and signals