Signal vs variable vs constant in VHDL - Visual Side-by-Side Comparison

Concept Flow - Signal vs variable vs constant

Start Process

↓

Declare constant

↓

Declare variable

↓

Declare signal

↓

Assign values

↓

Evaluate variable immediately

↓

Update signal at process end

↓

Use constant value anytime

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End Process

This flow shows how constants, variables, and signals are declared and updated inside a VHDL process, highlighting when their values change.

Execution Sample

VHDL

process
  constant C : integer := 5;
  variable V : integer := 0;
  signal S : integer := 0;
begin
  V := C + 1;
  S <= V + 1;
end process;

This VHDL process declares a constant, a variable, and a signal, then assigns values to variable and signal based on the constant and variable.

Execution Table

Step	Action	Constant C	Variable V	Signal S	Notes
1	Start process	5	0	0	Constant C initialized to 5, Variable V initialized to 0, Signal S initial value 0
2	Assign V := C + 1	5	6	0	Variable V updated immediately to 6
3	Assign S <= V + 1	5	6	0	Signal S scheduled to update to 7 at process end
4	End process - Signal update	5	6	7	Signal S updated to 7 after process completes

💡 Process ends, signal S updates after process, variable V updated immediately, constant C unchanged

Variable Tracker

Variable	Start	After Step 2	After Step 3	After Step 4 (final)
C (constant)	5	5	5	5
V (variable)	0	6	6	6
S (signal)	0	0	0	7

Key Moments - 3 Insights

Why does the variable V change immediately but the signal S does not?

Variables update instantly within the process (see Step 2), but signals schedule their update to happen only after the process ends (see Step 4). This means signal S keeps its old value during the process.

Can the constant C be changed during the process?

No, constants keep their value fixed throughout the process (see all steps in execution_table where C remains 5). You cannot assign a new value to a constant.

Why is the signal S value still 0 after assigning S <= V + 1 in Step 3?

Signal assignments inside a process do not take effect immediately; they are scheduled and updated only after the process finishes (see Step 4). So S remains 0 during the process.

Visual Quiz - 3 Questions

Look at the execution table, what is the value of variable V immediately after Step 2?

A 0

B 5

C 6

D undefined

💡 Hint

Check the 'Variable V' column at Step 2 in the execution_table.

At which step does the signal S actually update to its new value?

A Step 2

B Step 4

C Step 3

D Signal never updates

💡 Hint

Look at the 'Signal S' column in execution_table and see when it changes from 0 to 7.

If we tried to assign a new value to constant C inside the process, what would happen?

A Compilation error because constants cannot be changed

B C would update immediately like a variable

C C would update after the process like a signal

D C would keep old value but show a warning

💡 Hint

Refer to key_moments about constant behavior and immutability.

Concept Snapshot

VHDL constants hold fixed values and cannot change.
Variables update immediately inside a process.
Signals update only after the process ends.
Use constants for fixed values, variables for temporary immediate changes,
and signals for communication between processes.

Full Transcript

In VHDL, constants, variables, and signals behave differently inside a process. Constants are fixed and cannot be changed once declared. Variables update their values immediately when assigned inside the process. Signals, however, schedule their updates and only change after the process finishes. This means if you assign a new value to a signal inside a process, the old value remains during the process execution and the new value appears only after the process ends. This distinction is important for designing hardware behavior correctly. The example process shows a constant C set to 5, a variable V assigned C plus 1 immediately, and a signal S assigned V plus 1 but updated only after the process ends. Understanding these timing differences helps avoid bugs and design errors in VHDL code.