Signal vs variable vs constant in VHDL - Interactive Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a signal named 'clk' of type std_logic.

VHDL

signal clk : [1];

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Ainteger

Bboolean

Cbit_vector

Dstd_logic

Attempts:

3 left

💡 Hint

Common Mistakes

Using variable or constant keywords instead of signal.

Choosing an incorrect type like integer for a clock signal.

The keyword signal is used to declare signals in VHDL. Here, clk is declared as a signal of type std_logic, which is commonly used for clock signals.

2fill in blank

medium

Complete the code to declare a variable named 'temp' of type integer inside a process.

VHDL

process(clk)
  variable temp : [1];
begin
end process;

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Ainteger

Bbit

Cstd_logic

Dboolean

Attempts:

3 left

💡 Hint

Common Mistakes

Declaring variables outside processes.

Using signal types like std_logic for variables.

Variables inside processes are declared with the variable keyword and can have types like integer. Here, temp is an integer variable.

3fill in blank

hard

Fix the error in the constant declaration for a clock period of 10 ns.

VHDL

constant clock_period : time := [1];

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A10

B10ns

C10 ns

D"10 ns"

Attempts:

3 left

💡 Hint

Common Mistakes

Putting the time value in quotes.

Omitting the unit or space between number and unit.

Constants of type time require a value with units, like 10 ns. Quotation marks or missing spaces cause errors.

4fill in blank

hard

Fill both blanks to assign a value to a variable and a signal inside a process.

VHDL

process(clk) begin
  if rising_edge(clk) then
    temp := [1];
    output_signal <= [2];
  end if;
end process;

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A'1'

B'0'

Ctemp

Doutput_signal

Attempts:

3 left

💡 Hint

Common Mistakes

Using '<=' for variable assignment.

Using ':=' for signal assignment.

Variables use ':=' for assignment, and signals use '<=' inside processes. Here, temp is assigned '1' and output_signal is assigned '0'.

5fill in blank

hard

Fill all three blanks to create a dictionary comprehension-like construct using signals, variables, and constants.

VHDL

constant MAX_VAL : integer := [1];
signal flag : std_logic := [2];

process(clk)
  variable count : integer := 0;
begin
  if rising_edge(clk) then
    if count < MAX_VAL then
      count := count + 1;
      flag <= [3];
    end if;
  end if;
end process;

Drag options to blanks, or click blank then click option'

A100

B'0'

C'1'

D0

Attempts:

3 left

💡 Hint

Common Mistakes

Using integer 0 or 1 without quotes for std_logic signals.

Assigning signals with ':=' instead of '<='.

The constant MAX_VAL is set to 100. The signal flag is initialized to '0' and later assigned '1' inside the process. Variables use ':=' and signals use '<=' for assignment.