Signal vs variable vs constant in VHDL - Hands-On Comparison

Signal vs Variable vs Constant in VHDL

📖 Scenario: You are designing a simple VHDL process to understand how signals, variables, and constants behave differently inside a process block.This is like managing different types of notes in a notebook: some notes update immediately, some only after finishing a page, and some never change.

🎯 Goal: Build a VHDL process that declares a signal, a variable, and a constant. Then, update the signal and variable inside the process and observe their values at different points.This will help you see how signals and variables update differently and how constants remain fixed.

📋 What You'll Learn

Declare a signal called sig_count of type integer initialized to 0

Declare a constant called CONST_LIMIT of type integer with value 5

Inside a process, declare a variable called var_count of type integer initialized to 0

Inside the process, increment sig_count and var_count by 1

Print the values of sig_count and var_count inside the process

Print the value of sig_count outside the process after a wait statement

💡 Why This Matters

🌍 Real World

Understanding signals, variables, and constants is essential for designing reliable digital circuits and FPGA programming.

💼 Career

Hardware engineers and FPGA developers use these concepts daily to write efficient and correct VHDL code.

1

Declare the signal and constant

Declare a signal called sig_count of type integer initialized to 0 and a constant called CONST_LIMIT of type integer with value 5 in the architecture.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity demo is
    port (
        clk : in std_logic
    );
end demo;

architecture Behavioral of demo is
    -- Declare signal and constant here
    
begin

end Behavioral;

Need a hint?

Use signal sig_count : integer := 0; and constant CONST_LIMIT : integer := 5; inside the architecture before begin.

2

Declare the variable inside a process

Inside the architecture's begin block, create a process triggered by clk. Inside this process, declare a variable called var_count of type integer initialized to 0.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity demo is
    port (
        clk : in std_logic
    );
end demo;

architecture Behavioral of demo is
    signal sig_count : integer := 0;
    constant CONST_LIMIT : integer := 5;
begin
    process(clk)
        -- Declare variable var_count here
    begin
        if rising_edge(clk) then
            
        end if;
    end process;
end Behavioral;

Need a hint?

Inside the process, write variable var_count : integer := 0; before the begin of the process body.

3

Increment signal and variable inside the process

Inside the if rising_edge(clk) block, increment the signal sig_count by 1 using sig_count <= sig_count + 1; and increment the variable var_count by 1 using var_count := var_count + 1;.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity demo is
    port (
        clk : in std_logic
    );
end demo;

architecture Behavioral of demo is
    signal sig_count : integer := 0;
    constant CONST_LIMIT : integer := 5;
begin
    process(clk)
        variable var_count : integer := 0;
    begin
        if rising_edge(clk) then
            -- Increment signal and variable here
        end if;
    end process;
end Behavioral;

Need a hint?

Use sig_count <= sig_count + 1; to update the signal and var_count := var_count + 1; to update the variable inside the if rising_edge(clk) block.

4

Print values inside and outside the process

Inside the if rising_edge(clk) block, add report statements to print the current values of sig_count and var_count. Outside the process, add a wait for 10 ns; statement and then add a report statement to print the value of sig_count.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity demo is
    port (
        clk : in std_logic
    );
end demo;

architecture Behavioral of demo is
    signal sig_count : integer := 0;
    constant CONST_LIMIT : integer := 5;
begin
    process(clk)
        variable var_count : integer := 0;
    begin
        if rising_edge(clk) then
            sig_count <= sig_count + 1;
            var_count := var_count + 1;
            -- Add report statements here to print sig_count and var_count
        end if;
    end process;
    -- Add wait and report statement here to print sig_count outside the process
end Behavioral;

Need a hint?

Use report "Inside process: sig_count = " & integer'image(sig_count); and similarly for var_count. Outside the process, use wait for 10 ns; then report the signal value.