Signal vs variable vs constant in VHDL - Practice Questions

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output of this VHDL process?

Consider the following VHDL process. What will be the value of sig_out after the process executes?

VHDL

signal sig_out : integer := 0;
process
  variable var_temp : integer := 0;
begin
  var_temp := 5;
  sig_out <= var_temp;
  var_temp := 10;
  wait;
end process;

A sig_out = 5

B sig_out = 10

C sig_out = 0

D sig_out = undefined

💡 Hint

Remember that signals update after the process suspends, variables update immediately.

The variable var_temp changes immediately inside the process, but the signal sig_out only updates after the process suspends. The assignment sig_out <= var_temp; uses the value 5 at that moment. The later change to var_temp does not affect sig_out until the next process execution.

🧠 Conceptual

intermediate

Which statement about constants in VHDL is true?

Choose the correct statement about constants in VHDL.

A Constants can be assigned new values inside a process.

B Constants can be used to store temporary values inside a process.

C Constants must be initialized at declaration and cannot change.

D Constants behave like signals and update after a delta cycle.

💡 Hint

Think about the meaning of the word 'constant'.

Constants in VHDL must be initialized when declared and their values cannot be changed anywhere in the code. They are fixed throughout simulation.

🔧 Debug

advanced

Why does this VHDL code cause a simulation mismatch?

Given the following code snippet, why does the output signal not update as expected?

VHDL

signal clk : std_logic := '0';
signal out_sig : integer := 0;
process(clk)
  variable temp_var : integer := 0;
begin
  if rising_edge(clk) then
    temp_var := temp_var + 1;
    out_sig <= temp_var;
  end if;
end process;

A The signal <code>clk</code> is not toggling, so the process never runs.

B Signal <code>out_sig</code> cannot be assigned inside a clocked process.

C Variable <code>temp_var</code> resets to 0 on every clock cycle, so <code>out_sig</code> never increments.

D The process is missing a sensitivity list entry for <code>temp_var</code>.

💡 Hint

Is there code shown that toggles the clock signal?

No code is provided to toggle the clk signal. The process is sensitive only to clk, and at simulation time 0, rising_edge(clk) is false since clk = '0'. Thus, the process suspends without assigning to out_sig, and never resumes without clock edges. This causes out_sig to remain at 0, not updating as a counter might be expected to do.

📝 Syntax

advanced

Which option correctly declares a constant and uses it in a process?

Identify the correct VHDL code snippet that declares a constant and uses it inside a process.

A

signal MAX_VAL : integer := 10;
process
begin
  if input > MAX_VAL then
    output <= '1';
  end if;
  wait;
end process;

B

constant MAX_VAL : integer;
process
begin
  MAX_VAL := 10;
  if input > MAX_VAL then
    output <= '1';
  end if;
  wait;
end process;

C

variable MAX_VAL : integer := 10;
process
begin
  if input > MAX_VAL then
    output <= '1';
  end if;
  wait;
end process;

D

constant MAX_VAL : integer := 10;
process
begin
  if input > MAX_VAL then
    output <= '1';
  end if;
  wait;
end process;

💡 Hint

Remember how constants are declared and assigned in VHDL.

Option D correctly declares a constant with initialization and uses it inside a process. Option D tries to assign a value to a constant after declaration, which is illegal. Option D declares a signal, not a constant. Option D declares a variable outside a process, which is invalid.

🚀 Application

expert

How many times does the variable update inside this VHDL process?

Given the following process, how many times will var_count increment during one simulation cycle?

VHDL

process
  variable var_count : integer := 0;
begin
  var_count := var_count + 1;
  var_count := var_count + 1;
  var_count := var_count + 1;
  wait;
end process;

A Depends on the number of wait statements

B 3 times

C 0 times

D 1 time

💡 Hint

Variables update immediately within a process execution.

Variables update immediately in the process. Each assignment increments var_count by 1, so after three increments, var_count is 3 before the process suspends at wait.