Signal vs variable vs constant in VHDL - Practice Questions

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output of this VHDL process?

Consider the following VHDL process. What will be the value of sig_out after the process executes?

VHDL

signal sig_out : integer := 0;
process
  variable var_temp : integer := 0;
begin
  var_temp := 5;
  sig_out <= var_temp;
  var_temp := 10;
  wait;
end process;

A sig_out = 5

B sig_out = 10

C sig_out = 0

D sig_out = undefined

💡 Hint

Remember that signals update after the process suspends, variables update immediately.

The variable var_temp changes immediately inside the process, but the signal sig_out only updates after the process suspends. The assignment sig_out <= var_temp; uses the value 5 at that moment. The later change to var_temp does not affect sig_out until the next process execution.

🧠 Conceptual

intermediate

Which statement about constants in VHDL is true?

Choose the correct statement about constants in VHDL.

A Constants can be assigned new values inside a process.

B Constants can be used to store temporary values inside a process.

C Constants must be initialized at declaration and cannot change.

D Constants behave like signals and update after a delta cycle.

💡 Hint

Think about the meaning of the word 'constant'.

Constants in VHDL must be initialized when declared and their values cannot be changed anywhere in the code. They are fixed throughout simulation.

🔧 Debug

advanced

Why does this VHDL code cause a simulation mismatch?

Given the following code snippet, why does the output signal not update as expected?

VHDL

signal clk : std_logic := '0';
signal out_sig : integer := 0;
process(clk)
  variable temp_var : integer := 0;
begin
  if rising_edge(clk) then
    temp_var := temp_var + 1;
    out_sig <= temp_var;
  end if;
end process;

A The signal <code>clk</code> is not toggling, so the process never runs.

B Signal <code>out_sig</code> cannot be assigned inside a clocked process.

C Variable <code>temp_var</code> resets to 0 on every clock cycle, so <code>out_sig</code> never increments.

D The process is missing a sensitivity list entry for <code>temp_var</code>.

💡 Hint

Is there code shown that toggles the clock signal?

No code is provided to toggle the clk signal. The process is sensitive only to clk, and at simulation time 0, rising_edge(clk) is false since clk = '0'. Thus, the process suspends without assigning to out_sig, and never resumes without clock edges. This causes out_sig to remain at 0, not updating as a counter might be expected to do.

📝 Syntax

advanced

Which option correctly declares a constant and uses it in a process?

Identify the correct VHDL code snippet that declares a constant and uses it inside a process.

A

signal MAX_VAL : integer := 10;
process
begin
  if input > MAX_VAL then
    output <= '1';
  end if;
  wait;
end process;

B

constant MAX_VAL : integer;
process
begin
  MAX_VAL := 10;
  if input > MAX_VAL then
    output <= '1';
  end if;
  wait;
end process;

C

variable MAX_VAL : integer := 10;
process
begin
  if input > MAX_VAL then
    output <= '1';
  end if;
  wait;
end process;

D

constant MAX_VAL : integer := 10;
process
begin
  if input > MAX_VAL then
    output <= '1';
  end if;
  wait;
end process;

💡 Hint

Remember how constants are declared and assigned in VHDL.

Option D correctly declares a constant with initialization and uses it inside a process. Option D tries to assign a value to a constant after declaration, which is illegal. Option D declares a signal, not a constant. Option D declares a variable outside a process, which is invalid.

🚀 Application

expert

How many times does the variable update inside this VHDL process?

Given the following process, how many times will var_count increment during one simulation cycle?

VHDL

process
  variable var_count : integer := 0;
begin
  var_count := var_count + 1;
  var_count := var_count + 1;
  var_count := var_count + 1;
  wait;
end process;

A Depends on the number of wait statements

B 3 times

C 0 times

D 1 time

💡 Hint

Variables update immediately within a process execution.

Variables update immediately in the process. Each assignment increments var_count by 1, so after three increments, var_count is 3 before the process suspends at wait.

Practice

1. Which of the following best describes a signal in VHDL?

easy

A. It communicates between processes and updates after the process ends.

B. It holds a fixed value that never changes.

C. It is temporary and updates immediately inside a process.

D. It is used only for constants and cannot change.

Solution

1. Step 1: Understand the role of signals

   Signals are used to communicate between different processes in VHDL and their values update only after the process finishes executing.

2. Step 2: Compare with variables and constants

   Variables update immediately inside a process, and constants never change. Signals differ by updating after the process ends.

3. Final Answer:

   It communicates between processes and updates after the process ends. -> Option A

4. Quick Check:

   Signal = Communicates between processes [OK]

Hint: Signals update after process ends, variables update immediately [OK]

Common Mistakes:

• Confusing signals with variables updating immediately
• Thinking constants can change
• Assuming signals update instantly inside processes

2. Which of the following is the correct way to declare a constant in VHDL?

easy

A. variable MAX_VALUE : integer := 100;

B. signal MAX_VALUE : integer := 100;

C. const MAX_VALUE : integer := 100;

D. constant MAX_VALUE : integer := 100;

Solution

1. Step 1: Recall constant declaration syntax

   In VHDL, constants are declared using the keyword constant followed by the name, type, and value.

2. Step 2: Check each option

   constant MAX_VALUE : integer := 100; (D) uses constant correctly. A uses variable, B uses signal, and C uses an invalid keyword const.

3. Final Answer:

   constant MAX_VALUE : integer := 100; -> Option D

4. Quick Check:

   Constant declaration uses keyword 'constant' [OK]

Hint: Constants use keyword 'constant' not 'variable' or 'signal' [OK]

Common Mistakes:

• Using 'variable' or 'signal' instead of 'constant'
• Using 'const' which is not valid in VHDL
• Omitting the type or value in declaration

3. Consider the following VHDL process:

process
  variable temp : integer := 0;
  begin
    temp := temp + 1;
    output_signal <= temp;
end process;

What will be the value assigned to output_signal after the first process execution?

medium

A. 0

B. 1

C. Undefined

D. Error

Solution

1. Step 1: Understand variable and signal update timing

   The variable temp is initialized to 0 and updates immediately inside the process: temp := temp + 1; sets it to 1.

2. Step 2: Determine signal value after process

   The assignment output_signal <= temp; (temp=1) schedules the update to 1, which takes effect after the process ends. Thus, after the first execution, output_signal is 1.

3. Final Answer:

   1 -> Option B

4. Quick Check:

   Variable immediate, signal after process; output_signal = 1 [OK]

Hint: Signals update after process ends; variables update immediately [OK]

Common Mistakes:

• Thinking signal assignment schedules the old variable value (0)
• Confusing variable and signal update timing
• Expecting output_signal to remain 0 after process

4. Identify the error in the following VHDL code snippet:

process
  variable count : integer := 0;
begin
  count := count + 1;
  signal_flag <= count;
end process;

medium

A. No error; the code is correct.

B. Signals cannot be assigned inside a process.

C. Variables cannot be initialized inside a process.

D. Signal assignment uses '<=' but variable assignment uses ':='; mixing them is incorrect.

Solution

1. Step 1: Check variable declaration

   Variables can be declared and initialized in the process declarative region before begin, so C is wrong.

2. Step 2: Check assignment syntax

   Variables use :=, signals use <=; the code uses both correctly, so A (claiming mixing incorrect) is wrong.

3. Step 3: Check signal usage

   Signals must be assigned inside processes to drive them, so B is wrong.

4. Final Answer:

   No error; the code is correct. -> Option A

5. Quick Check:

   Correct syntax: decl before begin, proper operators [OK]

Hint: Remember '<=' for signals, ':=' for variables [OK]

Common Mistakes:

• Thinking variables can't be initialized inside processes
• Confusing signal and variable assignment operators
• Thinking mixing assignment operators is an error

5. You want to create a VHDL process that counts clock cycles and holds a fixed maximum count value. Which combination correctly uses signal, variable, and constant?

hard

A. Declare a signal MAX_COUNT, a constant count inside the process, and a variable output_count.

B. Declare a variable MAX_COUNT, a signal count inside the process, and a constant output_count.

C. Declare a constant MAX_COUNT, a variable count inside the process, and a signal output_count to communicate outside.

D. Declare all as variables inside the process.

Solution

1. Step 1: Understand roles of constant, variable, and signal

   The maximum count value should never change, so it must be a constant. The count that changes during process execution is best as a variable for immediate updates. The output count that communicates outside the process should be a signal.

2. Step 2: Match roles to options

   Declare a constant MAX_COUNT, a variable count inside the process, and a signal output_count to communicate outside. correctly assigns MAX_COUNT as constant, count as variable inside the process, and output_count as signal. Other options misuse these roles.

3. Final Answer:

   Declare a constant MAX_COUNT, a variable count inside the process, and a signal output_count to communicate outside. -> Option C

4. Quick Check:

   Constant fixed, variable immediate, signal communicates [OK]

Hint: Constant fixed, variable immediate, signal communicates outside [OK]

Common Mistakes:

• Using variable for fixed max count
• Using signal inside process for immediate updates
• Declaring all as variables ignoring constants and signals