Why Selected assignment (with-select) in VHDL? - Purpose & Use Cases

The Big Idea

What if you could replace long, confusing condition checks with a neat, simple block that does it all at once?

The Scenario

Imagine you have to assign different values to a signal based on many conditions, and you write a long chain of if-else statements for each case.

For example, setting output signals manually for each input value without a clear structure.

The Problem

This manual method is slow to write and hard to read.

It is easy to make mistakes, like missing a case or mixing up assignments.

When you want to change or add cases, you have to rewrite many lines, increasing errors.

The Solution

Selected assignment with with-select lets you assign values to a signal based on conditions in a clean, compact way.

It groups all cases together, making the code easier to read and maintain.

Adding or changing cases is simple and less error-prone.

Before vs After

✗ Before

if sel = "00" then
  out <= "0001";
elsif sel = "01" then
  out <= "0010";
else
  out <= "0000";
end if;

✓ After

with sel select
  out <= "0001" when "00",
         "0010" when "01",
         "0000" when others;

What It Enables

This lets you write clear, concise hardware descriptions that are easy to update and less prone to bugs.

Real Life Example

In a traffic light controller, you can assign light signals based on the current state using with-select, making the logic straightforward and easy to follow.

Key Takeaways

Manual if-else chains are hard to manage for multiple conditions.

with-select groups assignments clearly by condition.

It improves readability and reduces errors in hardware design.