Selected assignment (with-select) in VHDL - Deep Dive

Overview - Selected assignment (with-select)

What is it?

Selected assignment with 'with-select' in VHDL is a way to assign values to a signal based on the value of another signal. It lets you choose from multiple options and assign the corresponding value in a clear and concise way. This is useful for describing hardware behavior where different inputs lead to different outputs. It is a form of conditional assignment that is easy to read and write.

Why it matters

Without selected assignment, you would need many nested if-else statements or case statements, which can be harder to read and maintain. Selected assignment simplifies hardware description by making the logic clearer and less error-prone. It helps designers quickly map input conditions to outputs, improving productivity and reducing bugs in digital circuit design.

Where it fits

Before learning selected assignment, you should understand basic VHDL signals, data types, and simple assignments. After mastering selected assignment, you can learn more complex conditional statements like 'case' and 'if-then-else', and then move on to writing full hardware modules and state machines.

Mental Model

Core Idea

Selected assignment chooses one output value from many options based on the current input signal value.

Think of it like...

It's like a vending machine where you press a button (input), and the machine gives you the snack (output) that matches that button.

Input Signal ──┐
                │
                ▼
          ┌─────────────┐
          │ with-select │
          └─────────────┘
                │
                ▼
          Output Signal

Each input value maps to one output value.

Build-Up - 7 Steps

1

Foundation

Basic signal assignment in VHDL

Concept: How to assign a value to a signal in VHDL.

In VHDL, you assign a value to a signal using the '<=' operator. For example: signal_a <= '1'; This sets signal_a to logic 1.

Result

signal_a now holds the value '1'.

Understanding simple signal assignment is the foundation for all hardware description in VHDL.

2

Foundation

Understanding signal selection needs

Concept: Why we need to assign different values based on input signals.

Often, the output depends on the input. For example, if input = 0, output = 'A'; if input = 1, output = 'B'. Writing this with many if statements can be complex.

Result

Recognizing the need for a clearer way to assign outputs based on inputs.

Knowing the problem helps appreciate the solution that selected assignment provides.

3

Intermediate

Using 'with-select' syntax

🤔Before reading on: do you think 'with-select' can assign multiple outputs at once or only one output based on input? Commit to your answer.

Concept: 'with-select' assigns one output value chosen from many options based on an input signal.

Syntax example: with input_signal select output_signal <= '0' when "00", '1' when "01", 'Z' when others; This means output_signal depends on input_signal's value.

Result

output_signal changes automatically to the value matching input_signal.

Understanding the syntax unlocks writing concise conditional assignments.

4

Intermediate

Handling 'others' in selected assignment

🤔Before reading on: do you think 'others' covers only one value or multiple values not listed explicitly? Commit to your answer.

Concept: 'others' covers all input values not explicitly listed, ensuring completeness.

In the 'with-select' statement, 'others' acts as a catch-all for any input values not matched before. For example: with input_signal select output_signal <= '0' when "00", '1' when "01", 'Z' when others; Here, any input other than "00" or "01" sets output_signal to 'Z'.

Result

The design is safe and complete, avoiding undefined outputs.

Knowing 'others' prevents incomplete assignments that cause simulation or synthesis errors.

5

Intermediate

Difference between selected and conditional assignment

🤔Before reading on: do you think selected assignment is just a shortcut for if-else, or does it have different behavior? Commit to your answer.

Concept: Selected assignment chooses output based on one input signal's value, while conditional assignment can use complex boolean expressions.

Selected assignment example: with sel select out <= '0' when "00", '1' when "01", 'Z' when others; Conditional assignment example: out <= '1' when (a = '1' and b = '0') else '0'; Selected assignment is simpler when output depends on one signal's value; conditional is more flexible for complex conditions.

Result

You can choose the best assignment style for clarity and efficiency.

Understanding the difference helps write clearer and more maintainable VHDL code.

6

Advanced

Synthesizability and hardware mapping

🤔Before reading on: do you think 'with-select' always produces combinational logic, or can it infer sequential elements? Commit to your answer.

Concept: 'with-select' maps to combinational logic in hardware and is synthesizable for most FPGA and ASIC tools.

The 'with-select' statement describes combinational logic where output depends only on current input. Synthesis tools convert it into multiplexers or lookup tables. It cannot describe memory or sequential behavior by itself.

Result

Hardware generated is fast and predictable combinational logic.

Knowing the hardware implication helps avoid mistakes like expecting memory behavior from 'with-select'.

7

Expert

Subtle priority and multiple drivers issues

🤔Before reading on: do you think multiple 'with-select' assignments to the same signal combine automatically or cause conflicts? Commit to your answer.

Concept: Multiple 'with-select' assignments to the same signal cause conflicts; VHDL signals cannot have multiple drivers without resolution.

If you write: with sel1 select out <= '0' when "00", '1' when others; with sel2 select out <= 'Z' when "10", '1' when others; This causes multiple drivers on 'out', which is illegal unless 'out' is a resolved type like std_logic with resolution function. Usually, this leads to errors or unexpected behavior.

Result

Avoid multiple assignments to the same signal with 'with-select' to prevent conflicts.

Understanding signal driver rules prevents subtle bugs and synthesis errors in complex designs.

Under the Hood

'with-select' works by evaluating the input signal's current value and selecting the corresponding output value from the list. Internally, synthesis tools implement this as a multiplexer circuit, where the input signal acts as the selector lines. The output signal is driven by the selected input value. The 'others' clause ensures all possible input values are covered, preventing undefined states.

Why designed this way?

The 'with-select' statement was designed to provide a clear, concise way to describe multiplexing behavior in hardware. It avoids verbose if-else chains and makes the designer's intent explicit. Alternatives like nested if statements are more flexible but less readable. The selected assignment syntax aligns well with hardware multiplexers, making synthesis straightforward.

Input Signal ──────────────┐
                           │
          ┌──────────────┐  │
          │ Multiplexer  │◄─┘
          └──────────────┘
                 │
                 ▼
          Output Signal

Each input value selects one output value.

Myth Busters - 4 Common Misconceptions

Quick: Does 'with-select' allow multiple output values to be assigned simultaneously? Commit to yes or no.

Common Belief: People often think 'with-select' can assign multiple outputs at once based on one input.

Reality: 'with-select' assigns exactly one output value based on the input signal's current value.

Why it matters: Believing multiple outputs can be assigned leads to incorrect code and synthesis errors.

Quick: Is 'others' optional in 'with-select' statements? Commit to yes or no.

Common Belief: Some think 'others' is optional and can be left out if all cases are listed.

Reality: 'others' is required if not all possible input values are explicitly covered to avoid incomplete assignments.

Why it matters: Omitting 'others' causes simulation warnings and synthesis errors due to incomplete assignments.

Quick: Does 'with-select' infer sequential logic like flip-flops? Commit to yes or no.

Common Belief: Some believe 'with-select' can describe memory elements or sequential logic.

Reality: 'with-select' only describes combinational logic; it cannot infer flip-flops or latches.

Why it matters: Misusing 'with-select' for sequential logic leads to incorrect hardware behavior and design failures.

Quick: Can you safely assign the same signal multiple times with different 'with-select' statements? Commit to yes or no.

Common Belief: Some think multiple 'with-select' assignments to the same signal combine without issues.

Reality: Multiple assignments to the same signal cause conflicts unless the signal type supports resolution, which is rare and complex.

Why it matters: This misconception causes synthesis errors and unpredictable hardware behavior.

Expert Zone

1

Selected assignment is strictly concurrent and cannot be used inside processes, which affects how you structure your VHDL code.

2

The order of choices in 'with-select' does not affect priority; all choices are evaluated in parallel, unlike if-else chains.

3

Using 'others' with care is crucial; assigning a default value can mask missing cases and hide design bugs.

When NOT to use

Avoid 'with-select' when output depends on multiple signals or complex boolean expressions; use conditional assignments or processes instead. Also, do not use it for sequential logic; use clocked processes for that.

Production Patterns

In real-world designs, 'with-select' is commonly used for multiplexers, simple decoders, and signal routing logic. It is favored for its clarity and direct hardware mapping, especially in FPGA designs where LUTs implement multiplexers efficiently.

Connections

Multiplexer (Hardware)

'with-select' directly models a multiplexer circuit in hardware.

Understanding multiplexers in hardware helps grasp why 'with-select' is a natural and efficient way to describe selection logic in VHDL.

Switch-case statements (Programming)

'with-select' is similar to switch-case in software programming languages.

Knowing switch-case helps programmers quickly understand 'with-select' as a way to select output based on discrete input values.

Decision Trees (Machine Learning)

'with-select' resembles a simple decision tree where one input decides the output branch.

Recognizing this connection shows how selection logic is a fundamental pattern across fields, from hardware to AI.

Common Pitfalls

#1 Incomplete coverage of input values causing undefined outputs.

Wrong approach:

with sel select
out <= '0' when "00",
'1' when "01";
-- Missing 'others' clause

Correct approach:

with sel select
out <= '0' when "00",
'1' when "01",
'Z' when others;

Root cause:

Not including 'others' leads to incomplete assignments, which synthesis tools reject or simulate incorrectly.

#2 Assigning the same signal multiple times with 'with-select' causing conflicts.

Wrong approach:

with sel1 select
out <= '0' when "00",
'1' when others;
with sel2 select
out <= 'Z' when "10",
'1' when others;

Correct approach:

Combine all conditions into one 'with-select' or use a process to assign 'out' once.

Root cause:

Signals in VHDL cannot have multiple concurrent drivers without resolution, causing conflicts.

#3 Using 'with-select' inside a process block incorrectly.

Wrong approach:

process(clk) begin
with sel select
out <= '0' when "00",
'1' when others;
end process;

Correct approach:

process(clk) begin
if rising_edge(clk) then
case sel is
when "00" => out <= '0';
when others => out <= '1';
end case;
end if;
end process;

Root cause:

'with-select' is a concurrent statement and cannot be used inside processes.

Key Takeaways

'with-select' is a concise way to assign one output value based on one input signal's value in VHDL.

It models combinational multiplexing logic and is synthesizable to hardware efficiently.

Always include the 'others' clause to cover all input cases and avoid incomplete assignments.

Avoid multiple 'with-select' assignments to the same signal to prevent driver conflicts.

Use 'with-select' for simple selection logic; use conditional assignments or processes for complex or sequential logic.