Recall & Review
beginner
What is a selected assignment in VHDL?
A selected assignment in VHDL is a way to assign values to a signal based on the value of another signal, using the
with-select statement. It is like a switch-case for signals.Click to reveal answer
beginner
Write the syntax structure of a selected assignment using
with-select.The syntax is:
with <expression> select
<target_signal> <assignment_operator> <value_1> when <choice_1>,
<value_2> when <choice_2>,
...
<default_value> when others;
Click to reveal answer
beginner
What happens if none of the choices in a selected assignment match the expression value?
The value assigned is the one specified by the
when others clause, which acts as a default case to cover all unmatched values.Click to reveal answer
intermediate
Can a selected assignment be used for signals of any type?
No, the expression used in
with-select must be of a discrete type like enumeration, integer, or std_logic, and the choices must cover all possible values or use when others.Click to reveal answer
beginner
Example: What is the output of this code?
If
with sel select
out_sig <= '1' when '1',
'0' when others;
If
sel = '0'?The output
out_sig will be '0' because sel is '0' and the when others clause covers all values except '1'.Click to reveal answer
What keyword is used in VHDL for selected assignment?
✗ Incorrect
The
with-select statement is used for selected assignments in VHDL.In a selected assignment, what does
when others mean?✗ Incorrect
when others covers all values not explicitly listed, acting as a default.Which of these is NOT valid in a selected assignment expression?
✗ Incorrect
Real numbers are not discrete types and cannot be used in selected assignments.
What happens if you omit
when others and not all values are covered?✗ Incorrect
VHDL requires all possible values to be covered; otherwise, it causes a compilation error.
Which signal type is commonly used with selected assignment?
✗ Incorrect
Selected assignment works with any discrete type like integer, boolean, or std_logic.
Explain how a selected assignment with
with-select works in VHDL.Think of it like choosing an output based on a signal's value.
You got /4 concepts.
Describe the importance of the
when others clause in selected assignments.What happens if the expression value is not listed explicitly?
You got /3 concepts.