Selected assignment (with-select) in VHDL - Mini Project: Build & Apply

Selected Assignment Using with-select in VHDL

📖 Scenario: You are designing a simple digital circuit that outputs a specific 4-bit value based on a 2-bit input selector. This is a common task in digital design where you want to choose one of several values depending on a control signal.

🎯 Goal: Build a VHDL code snippet that uses a with-select statement to assign a 4-bit output signal based on a 2-bit input selector signal.

📋 What You'll Learn

Create a 2-bit input signal called sel.

Create a 4-bit output signal called out_val.

Use a with sel select statement to assign out_val based on sel.

Assign these exact values for out_val: "0001" for sel = "00", "0010" for sel = "01", "0100" for sel = "10", and "1000" for sel = "11".

💡 Why This Matters

🌍 Real World

Selected assignment with <code>with-select</code> is used in digital circuits to choose one output from many inputs based on control signals, like multiplexers.

💼 Career

Understanding <code>with-select</code> statements is essential for hardware engineers and FPGA designers to write clear and efficient VHDL code.

1

Create input and output signals

Declare a 2-bit input signal called sel and a 4-bit output signal called out_val inside an architecture.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity selector is
    Port (
        sel : in std_logic_vector(1 downto 0);
        out_val : out std_logic_vector(3 downto 0)
    );
end selector;

architecture Behavioral of selector is
begin
    -- Declare signals sel and out_val are already declared in entity
    -- Your code here
end Behavioral;

Need a hint?

Remember, input and output signals are declared in the entity port list.

2

Add with-select statement

Inside the architecture body, write a with sel select statement to assign out_val based on sel.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity selector is
    Port (
        sel : in std_logic_vector(1 downto 0);
        out_val : out std_logic_vector(3 downto 0)
    );
end selector;

architecture Behavioral of selector is
begin
    -- Add with-select statement to assign out_val based on sel
    -- Your code here
end Behavioral;

Need a hint?

Use the syntax: with sel select out_val <= value when condition, ...;

3

Assign exact values for each selector case

Complete the with sel select statement by assigning out_val the exact values: "0001" for sel = "00", "0010" for sel = "01", "0100" for sel = "10", and "1000" for sel = "11".

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity selector is
    Port (
        sel : in std_logic_vector(1 downto 0);
        out_val : out std_logic_vector(3 downto 0)
    );
end selector;

architecture Behavioral of selector is
begin
    -- Assign exact values for out_val using with-select
    -- Your code here
end Behavioral;

Need a hint?

Make sure each when condition matches the exact selector value and output.

4

Test output with a print statement (simulation)

Add a simple process to print the value of out_val for each sel value in a testbench style process. Print the output using report statements for sel values "00", "01", "10", and "11".

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity selector is
    Port (
        sel : in std_logic_vector(1 downto 0);
        out_val : out std_logic_vector(3 downto 0)
    );
end selector;

architecture Behavioral of selector is
begin
    with sel select
        out_val <= "0001" when "00",
                   "0010" when "01",
                   "0100" when "10",
                   "1000" when "11";

    -- Add a process to simulate and print out_val for each sel
    -- Your code here
end Behavioral;

Need a hint?

Use a process with a loop to assign sel values and print out_val using report.