Decoder and encoder design in VHDL - Step-by-Step Execution

Concept Flow - Decoder and encoder design

Input bits

↓

Decoder: 2^n outputs

↓

One output active

↓

Input lines

↓

Encoder: n outputs

↓

Binary code output

A decoder takes n input bits and activates one of 2^n outputs. An encoder does the opposite: it takes one active input line and outputs the corresponding binary code.

Execution Sample

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Decoder2to4 is
  Port ( A : in STD_LOGIC_VECTOR(1 downto 0);
         Y : out STD_LOGIC_VECTOR(3 downto 0));
end Decoder2to4;

This VHDL code defines a 2-to-4 line decoder entity with 2 input bits and 4 output lines.

Execution Table

Step	Input A(1 downto 0)	Decoder Output Y(3 downto 0)	Explanation
1	"00"	"0001"	Input 00 activates output Y0 only
2	"01"	"0010"	Input 01 activates output Y1 only
3	"10"	"0100"	Input 10 activates output Y2 only
4	"11"	"1000"	Input 11 activates output Y3 only
5	Any other	"0000"	No output active (default)

💡 All possible 2-bit inputs covered; decoder outputs one active line per input.

Variable Tracker

Variable	Start	After Step 1	After Step 2	After Step 3	After Step 4	Final
A	"00"	"00"	"01"	"10"	"11"	"11"
Y	"0000"	"0001"	"0010"	"0100"	"1000"	"1000"

Key Moments - 3 Insights

Why does only one output line go high for each input in the decoder?

Because the decoder activates exactly one output line corresponding to the binary input, as shown in execution_table rows 1-4.

What happens if the input to the decoder is invalid or not covered?

The decoder outputs all zeros (no active output), as shown in execution_table row 5.

How does the encoder know which input line is active?

The encoder detects the single active input line and outputs its binary code, the reverse of the decoder process.

Visual Quiz - 3 Questions

Look at the execution_table, what is the decoder output Y when input A is "10"?

A "0100"

B "0010"

C "1000"

D "0001"

💡 Hint

Check execution_table row 3 for input "10" and output Y.

At which step does the decoder output activate the third output line?

A Step 1

B Step 2

C Step 3

D Step 4

💡 Hint

Look at execution_table outputs and match the active bit position.

If the input A changes from "01" to "11", how does the output Y change?

A From "0001" to "0100"

B From "0010" to "1000"

C From "0100" to "0010"

D No change

💡 Hint

Compare execution_table rows 2 and 4 for inputs "01" and "11".

Concept Snapshot

Decoder:
- Input: n bits
- Output: 2^n lines
- Only one output active per input

Encoder:
- Input: one active line
- Output: n bits
- Outputs binary code of active input

Used for data routing and signal conversion.

Full Transcript

This visual execution shows how a 2-to-4 line decoder works in VHDL. The decoder takes 2 input bits and activates exactly one of 4 output lines. Each input combination corresponds to one output line going high. The variable tracker shows how inputs and outputs change step by step. Key moments clarify why only one output is active and what happens with invalid inputs. The quiz tests understanding of output values and transitions. The snapshot summarizes decoder and encoder roles in digital design.

Practice

1.

What is the main function of a decoder in VHDL?

easy

A. It converts a binary input code into one active output line.

B. It compresses multiple output lines into a smaller input code.

C. It stores data temporarily in registers.

D. It performs arithmetic operations on input signals.

Solution

1. Step 1: Understand the role of a decoder

   A decoder takes a small binary input and activates exactly one output line corresponding to that input.

2. Step 2: Compare with other options

   Options A, B, and C describe other components or functions, not a decoder's main role.

3. Final Answer:

   It converts a binary input code into one active output line. -> Option A

4. Quick Check:

   Decoder = binary input to one active output [OK]

Hint: Decoder activates one output from input code [OK]

Common Mistakes:

• Confusing decoder with encoder
• Thinking decoder stores data
• Assuming decoder performs arithmetic

2.

Which of the following is the correct VHDL syntax to declare a 2-to-4 decoder output signal named Y as a 4-bit std_logic_vector?

easy

A. signal Y : std_logic_vector(3 downto 1);

B. signal Y : std_logic_vector(0 downto 3);

C. signal Y : std_logic_vector(3 downto 0);

D. signal Y : std_logic_vector(4 to 1);

Solution

1. Step 1: Understand std_logic_vector indexing

   In VHDL, vectors are often declared with 'downto' for descending indices, so 3 downto 0 means 4 bits indexed 3,2,1,0.

2. Step 2: Check options for correct 4-bit declaration

   signal Y : std_logic_vector(3 downto 0); uses '3 downto 0' which is standard and correct. The other options are incorrect: B '0 downto 3' (invalid direction), C '3 downto 1' (3 bits), D '4 to 1' (invalid direction).

3. Final Answer:

   signal Y : std_logic_vector(3 downto 0); -> Option C

4. Quick Check:

   4-bit vector usually declared as 3 downto 0 [OK]

Hint: Use 'downto' for descending bit order in vectors [OK]

Common Mistakes:

• Using incorrect index ranges
• Confusing 'to' and 'downto' keywords
• Declaring wrong vector size

3.

Given the following VHDL code for a 2-to-4 decoder, what is the output Y when input A = "10"?

process(A)
begin
  case A is
    when "00" => Y <= "0001";
    when "01" => Y <= "0010";
    when "10" => Y <= "0100";
    when "11" => Y <= "1000";
    when others => Y <= "0000";
  end case;
end process;

medium

A. "0100"

B. "0010"

C. "0001"

D. "1000"

Solution

1. Step 1: Match input A with case branches

   The input A is "10", so the case statement matches the third when clause: when "10" => Y <= "0100".

2. Step 2: Confirm output value

   The output Y is assigned "0100" for input "10".

3. Final Answer:

   "0100" -> Option A

4. Quick Check:

   Input "10" activates third output "0100" [OK]

Hint: Match input bits exactly in case statement [OK]

Common Mistakes:

• Mixing up binary input values
• Choosing output for wrong input
• Ignoring 'when others' clause

4.

Identify the error in this VHDL code snippet for a 4-to-2 encoder:

process(I)
begin
  if I = "0001" then Y <= "00";
  elsif I = "0010" then Y <= "01";
  elsif I = "0100" then Y <= "10";
  elsif I = "1000" then Y <= "11";
  else Y <= "00";
end if;
end process;

medium

A. Input I should be declared as std_logic_vector(3 downto 0).

B. The code does not handle multiple active inputs correctly.

C. The process sensitivity list should include Y.

D. The output Y should be declared as std_logic_vector(3 downto 0).

Solution

1. Step 1: Analyze input and output declarations

   Input I is likely a 4-bit vector representing active lines; output Y is 2 bits encoding which input is active.

2. Step 2: Check logic for multiple active inputs

   The code assumes only one input bit is active at a time. It does not handle cases where multiple bits in I are '1', which is invalid for an encoder.

3. Step 3: Review other options

   Input I should be declared as std_logic_vector(3 downto 0). is likely true but not an error in this snippet. The process sensitivity list should include Y. is incorrect; Y should not be in sensitivity list. The output Y should be declared as std_logic_vector(3 downto 0). is wrong because Y is 2 bits, not 4.

4. Final Answer:

   The code does not handle multiple active inputs correctly. -> Option B

5. Quick Check:

   Encoder needs single active input line [OK]

Hint: Encoder requires only one active input line [OK]

Common Mistakes:

• Ignoring multiple active inputs
• Incorrect sensitivity list
• Wrong output size declaration

5.

You need to design a 3-to-8 decoder in VHDL that activates one output line based on a 3-bit input A. Which of the following code snippets correctly implements this decoder?

process(A)
begin
  Y <= (others => '0');
  case A is
    when "000" => Y(0) <= '1';
    when "001" => Y(1) <= '1';
    when "010" => Y(2) <= '1';
    when "011" => Y(3) <= '1';
    when "100" => Y(4) <= '1';
    when "101" => Y(5) <= '1';
    when "110" => Y(6) <= '1';
    when "111" => Y(7) <= '1';
    when others => Y <= (others => '0');
  end case;
end process;

hard

A. The case statement syntax is invalid in VHDL.

B. The code incorrectly sets multiple outputs high simultaneously.

C. The code misses resetting outputs before setting one high.

D. This code correctly sets one output bit high and resets others to zero.

Solution

1. Step 1: Check output initialization

   The line 'Y <= (others => '0');' sets all outputs to zero before activating one output line.

2. Step 2: Verify case statement logic

   Each case sets exactly one bit of Y to '1' based on input A, which is correct for a decoder.

3. Step 3: Confirm syntax correctness

   The case statement and assignments follow proper VHDL syntax.

4. Final Answer:

   This code correctly sets one output bit high and resets others to zero. -> Option D

5. Quick Check:

   Initialize outputs then activate one line [OK]

Hint: Reset outputs before setting one active bit [OK]

Common Mistakes:

• Not resetting outputs before setting one
• Setting multiple outputs high
• Incorrect case statement syntax