Decoder and encoder design in VHDL - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a 2-to-4 decoder output signal.

VHDL

signal output_lines : std_logic_vector([1] downto 0);

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A2

B4

C1

D3

Attempts:

3 left

💡 Hint

Common Mistakes

Using 4 downto 0 which creates 5 lines.

Using 2 downto 0 which creates 3 lines.

The output of a 2-to-4 decoder has 4 lines, indexed from 3 down to 0.

2fill in blank

medium

Complete the code to assign the output of a 2-to-4 decoder based on input bits.

VHDL

output_lines <= ("0001" when input_bits = "00" else
"0010" when input_bits = "01" else
"0100" when input_bits = "10" else
[1]);

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A"0000"

B"1000"

C"1111"

D"0011"

Attempts:

3 left

💡 Hint

Common Mistakes

Using "0000" which turns off all outputs.

Using "1111" which activates all outputs.

The last case for input_bits = "11" should activate the last output line, which is "1000".

3fill in blank

hard

Fix the error in the encoder process sensitivity list.

VHDL

process([1])
begin
  case input_lines is
    when "0001" => output_bits <= "00";
    when "0010" => output_bits <= "01";
    when "0100" => output_bits <= "10";
    when "1000" => output_bits <= "11";
    when others => output_bits <= "00";
  end case;
end process;

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Ainput_lines

Boutput_bits

Cclk

Dreset

Attempts:

3 left

💡 Hint

Common Mistakes

Using clk or reset which are unrelated signals here.

The process sensitivity list must include the signal that triggers the process, which is input_lines.

4fill in blank

hard

Fill both blanks to complete the 3-to-8 decoder output assignment with enable.

VHDL

with input_bits select
  output_lines <= [1] when "000",
                  [2] when others;

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A"00000001"

B"00000000"

C"11111111"

D"00000010"

Attempts:

3 left

💡 Hint

Common Mistakes

Using "11111111" for others which activates all outputs.

When input_bits is "000", only the first output line is high "00000001"; otherwise, all outputs are low "00000000".

5fill in blank

hard

Fill all three blanks to complete the priority encoder output logic.

VHDL

process(input_lines)
begin
  if input_lines([1]) = '1' then
    output_bits <= "[2]";
  elsif input_lines([3]) = '1' then
    output_bits <= "01";
  else
    output_bits <= "00";
  end if;
end process;

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A3

B10

C2

D11

Attempts:

3 left

💡 Hint

Common Mistakes

Mixing output codes or bit indices.

The highest priority input is bit 3, outputting "11"; next priority is bit 2, outputting "01".