Decoder and encoder design in VHDL - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a 2-to-4 decoder output signal.

VHDL

signal output_lines : std_logic_vector([1] downto 0);

Drag options to blanks, or click blank then click option'

A2

B4

C1

D3

Attempts:

3 left

💡 Hint

Common Mistakes

Using 4 downto 0 which creates 5 lines.

Using 2 downto 0 which creates 3 lines.

The output of a 2-to-4 decoder has 4 lines, indexed from 3 down to 0.

2fill in blank

medium

Complete the code to assign the output of a 2-to-4 decoder based on input bits.

VHDL

output_lines <= ("0001" when input_bits = "00" else
"0010" when input_bits = "01" else
"0100" when input_bits = "10" else
[1]);

Drag options to blanks, or click blank then click option'

A"0000"

B"1000"

C"1111"

D"0011"

Attempts:

3 left

💡 Hint

Common Mistakes

Using "0000" which turns off all outputs.

Using "1111" which activates all outputs.

The last case for input_bits = "11" should activate the last output line, which is "1000".

3fill in blank

hard

Fix the error in the encoder process sensitivity list.

VHDL

process([1])
begin
  case input_lines is
    when "0001" => output_bits <= "00";
    when "0010" => output_bits <= "01";
    when "0100" => output_bits <= "10";
    when "1000" => output_bits <= "11";
    when others => output_bits <= "00";
  end case;
end process;

Drag options to blanks, or click blank then click option'

Ainput_lines

Boutput_bits

Cclk

Dreset

Attempts:

3 left

💡 Hint

Common Mistakes

Using clk or reset which are unrelated signals here.

The process sensitivity list must include the signal that triggers the process, which is input_lines.

4fill in blank

hard

Fill both blanks to complete the 3-to-8 decoder output assignment with enable.

VHDL

with input_bits select
  output_lines <= [1] when "000",
                  [2] when others;

Drag options to blanks, or click blank then click option'

A"00000001"

B"00000000"

C"11111111"

D"00000010"

Attempts:

3 left

💡 Hint

Common Mistakes

Using "11111111" for others which activates all outputs.

When input_bits is "000", only the first output line is high "00000001"; otherwise, all outputs are low "00000000".

5fill in blank

hard

Fill all three blanks to complete the priority encoder output logic.

VHDL

process(input_lines)
begin
  if input_lines([1]) = '1' then
    output_bits <= "[2]";
  elsif input_lines([3]) = '1' then
    output_bits <= "01";
  else
    output_bits <= "00";
  end if;
end process;

Drag options to blanks, or click blank then click option'

A3

B10

C2

D11

Attempts:

3 left

💡 Hint

Common Mistakes

Mixing output codes or bit indices.

The highest priority input is bit 3, outputting "11"; next priority is bit 2, outputting "01".

Practice

1.

What is the main function of a decoder in VHDL?

easy

A. It converts a binary input code into one active output line.

B. It compresses multiple output lines into a smaller input code.

C. It stores data temporarily in registers.

D. It performs arithmetic operations on input signals.

Solution

1. Step 1: Understand the role of a decoder

   A decoder takes a small binary input and activates exactly one output line corresponding to that input.

2. Step 2: Compare with other options

   Options A, B, and C describe other components or functions, not a decoder's main role.

3. Final Answer:

   It converts a binary input code into one active output line. -> Option A

4. Quick Check:

   Decoder = binary input to one active output [OK]

Hint: Decoder activates one output from input code [OK]

Common Mistakes:

• Confusing decoder with encoder
• Thinking decoder stores data
• Assuming decoder performs arithmetic

2.

Which of the following is the correct VHDL syntax to declare a 2-to-4 decoder output signal named Y as a 4-bit std_logic_vector?

easy

A. signal Y : std_logic_vector(3 downto 1);

B. signal Y : std_logic_vector(0 downto 3);

C. signal Y : std_logic_vector(3 downto 0);

D. signal Y : std_logic_vector(4 to 1);

Solution

1. Step 1: Understand std_logic_vector indexing

   In VHDL, vectors are often declared with 'downto' for descending indices, so 3 downto 0 means 4 bits indexed 3,2,1,0.

2. Step 2: Check options for correct 4-bit declaration

   signal Y : std_logic_vector(3 downto 0); uses '3 downto 0' which is standard and correct. The other options are incorrect: B '0 downto 3' (invalid direction), C '3 downto 1' (3 bits), D '4 to 1' (invalid direction).

3. Final Answer:

   signal Y : std_logic_vector(3 downto 0); -> Option C

4. Quick Check:

   4-bit vector usually declared as 3 downto 0 [OK]

Hint: Use 'downto' for descending bit order in vectors [OK]

Common Mistakes:

• Using incorrect index ranges
• Confusing 'to' and 'downto' keywords
• Declaring wrong vector size

3.

Given the following VHDL code for a 2-to-4 decoder, what is the output Y when input A = "10"?

process(A)
begin
  case A is
    when "00" => Y <= "0001";
    when "01" => Y <= "0010";
    when "10" => Y <= "0100";
    when "11" => Y <= "1000";
    when others => Y <= "0000";
  end case;
end process;

medium

A. "0100"

B. "0010"

C. "0001"

D. "1000"

Solution

1. Step 1: Match input A with case branches

   The input A is "10", so the case statement matches the third when clause: when "10" => Y <= "0100".

2. Step 2: Confirm output value

   The output Y is assigned "0100" for input "10".

3. Final Answer:

   "0100" -> Option A

4. Quick Check:

   Input "10" activates third output "0100" [OK]

Hint: Match input bits exactly in case statement [OK]

Common Mistakes:

• Mixing up binary input values
• Choosing output for wrong input
• Ignoring 'when others' clause

4.

Identify the error in this VHDL code snippet for a 4-to-2 encoder:

process(I)
begin
  if I = "0001" then Y <= "00";
  elsif I = "0010" then Y <= "01";
  elsif I = "0100" then Y <= "10";
  elsif I = "1000" then Y <= "11";
  else Y <= "00";
end if;
end process;

medium

A. Input I should be declared as std_logic_vector(3 downto 0).

B. The code does not handle multiple active inputs correctly.

C. The process sensitivity list should include Y.

D. The output Y should be declared as std_logic_vector(3 downto 0).

Solution

1. Step 1: Analyze input and output declarations

   Input I is likely a 4-bit vector representing active lines; output Y is 2 bits encoding which input is active.

2. Step 2: Check logic for multiple active inputs

   The code assumes only one input bit is active at a time. It does not handle cases where multiple bits in I are '1', which is invalid for an encoder.

3. Step 3: Review other options

   Input I should be declared as std_logic_vector(3 downto 0). is likely true but not an error in this snippet. The process sensitivity list should include Y. is incorrect; Y should not be in sensitivity list. The output Y should be declared as std_logic_vector(3 downto 0). is wrong because Y is 2 bits, not 4.

4. Final Answer:

   The code does not handle multiple active inputs correctly. -> Option B

5. Quick Check:

   Encoder needs single active input line [OK]

Hint: Encoder requires only one active input line [OK]

Common Mistakes:

• Ignoring multiple active inputs
• Incorrect sensitivity list
• Wrong output size declaration

5.

You need to design a 3-to-8 decoder in VHDL that activates one output line based on a 3-bit input A. Which of the following code snippets correctly implements this decoder?

process(A)
begin
  Y <= (others => '0');
  case A is
    when "000" => Y(0) <= '1';
    when "001" => Y(1) <= '1';
    when "010" => Y(2) <= '1';
    when "011" => Y(3) <= '1';
    when "100" => Y(4) <= '1';
    when "101" => Y(5) <= '1';
    when "110" => Y(6) <= '1';
    when "111" => Y(7) <= '1';
    when others => Y <= (others => '0');
  end case;
end process;

hard

A. The case statement syntax is invalid in VHDL.

B. The code incorrectly sets multiple outputs high simultaneously.

C. The code misses resetting outputs before setting one high.

D. This code correctly sets one output bit high and resets others to zero.

Solution

1. Step 1: Check output initialization

   The line 'Y <= (others => '0');' sets all outputs to zero before activating one output line.

2. Step 2: Verify case statement logic

   Each case sets exactly one bit of Y to '1' based on input A, which is correct for a decoder.

3. Step 3: Confirm syntax correctness

   The case statement and assignments follow proper VHDL syntax.

4. Final Answer:

   This code correctly sets one output bit high and resets others to zero. -> Option D

5. Quick Check:

   Initialize outputs then activate one line [OK]

Hint: Reset outputs before setting one active bit [OK]

Common Mistakes:

• Not resetting outputs before setting one
• Setting multiple outputs high
• Incorrect case statement syntax