Decoder and encoder design in VHDL - Mini Project: Build & Apply

Decoder and Encoder Design in VHDL

📖 Scenario: You are designing simple digital circuits that convert signals from one form to another. A decoder takes a small number of input bits and activates one output line based on the input. An encoder does the opposite: it takes multiple input lines and converts them into a smaller number of output bits.These circuits are used in many electronics devices, like remote controls, keyboards, and communication systems.

🎯 Goal: You will create a 2-to-4 line decoder and a 4-to-2 line encoder using VHDL. You will write the code step-by-step, starting with inputs and outputs, then adding the logic, and finally displaying the output signals.

📋 What You'll Learn

Create a 2-to-4 line decoder entity with inputs input_bits (2 bits) and outputs decoder_out (4 bits).

Create a 4-to-2 line encoder entity with inputs encoder_in (4 bits) and outputs encoded_out (2 bits).

Use simple combinational logic (with when or with-select statements) for both decoder and encoder.

Print or simulate the output signals to verify correct behavior.

💡 Why This Matters

🌍 Real World

Decoders and encoders are basic building blocks in digital electronics used in devices like keyboards, multiplexers, and communication systems to convert signals between different formats.

💼 Career

Understanding how to design and implement decoders and encoders in VHDL is essential for hardware engineers working on FPGA or ASIC design, embedded systems, and digital circuit development.

1

Create the 2-to-4 Decoder Entity and Architecture

Write VHDL code to create an entity called decoder_2to4 with a 2-bit input port named input_bits and a 4-bit output port named decoder_out. Then start the architecture named behavior.

VHDL

-- Your code here to define entity decoder_2to4 and architecture behavior

Hint

Remember to declare the entity with input and output ports exactly as named.

2

Add Decoder Logic Using with-select Statement

Inside the behavior architecture, write a with input_bits select statement to assign decoder_out so that only one bit is '1' corresponding to the binary value of input_bits, and others are '0'. For example, if input_bits is "00", decoder_out should be "0001".

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity decoder_2to4 is
    Port ( input_bits : in STD_LOGIC_VECTOR(1 downto 0);
           decoder_out : out STD_LOGIC_VECTOR(3 downto 0));
end decoder_2to4;

architecture behavior of decoder_2to4 is
begin
-- Add with-select statement for decoder_out here

Hint

Use the with-select statement to assign output patterns for each input.

3

Create the 4-to-2 Encoder Entity and Architecture

Write VHDL code to create an entity called encoder_4to2 with a 4-bit input port named encoder_in and a 2-bit output port named encoded_out. Then start the architecture named behavior.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity decoder_2to4 is
    Port ( input_bits : in STD_LOGIC_VECTOR(1 downto 0);
           decoder_out : out STD_LOGIC_VECTOR(3 downto 0));
end decoder_2to4;

architecture behavior of decoder_2to4 is
begin
    with input_bits select
        decoder_out <= "0001" when "00",
                       "0010" when "01",
                       "0100" when "10",
                       "1000" when "11",
                       "0000" when others;
end behavior;

-- Your code here to define entity encoder_4to2 and architecture behavior

Hint

Define the encoder entity and architecture with the exact port names and sizes.

4

Add Encoder Logic Using with-select Statement and Display Output

Inside the behavior architecture of encoder_4to2, write a with encoder_in select statement to assign encoded_out so that it outputs the binary index of the input bit that is '1'. For example, if encoder_in is "0001", encoded_out should be "00". Then add a process or statement to print the encoded output for the input "0100".

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity decoder_2to4 is
    Port ( input_bits : in STD_LOGIC_VECTOR(1 downto 0);
           decoder_out : out STD_LOGIC_VECTOR(3 downto 0));
end decoder_2to4;

architecture behavior of decoder_2to4 is
begin
    with input_bits select
        decoder_out <= "0001" when "00",
                       "0010" when "01",
                       "0100" when "10",
                       "1000" when "11",
                       "0000" when others;
end behavior;

entity encoder_4to2 is
    Port ( encoder_in : in STD_LOGIC_VECTOR(3 downto 0);
           encoded_out : out STD_LOGIC_VECTOR(1 downto 0));
end encoder_4to2;

architecture behavior of encoder_4to2 is
begin
-- Add with-select statement for encoded_out here

-- Add a simple process to print encoded_out for input "0100"

Hint

Use with-select to assign encoded_out. Use a process with write and writeline to print the output.

Practice

1.

What is the main function of a decoder in VHDL?

easy

A. It converts a binary input code into one active output line.

B. It compresses multiple output lines into a smaller input code.

C. It stores data temporarily in registers.

D. It performs arithmetic operations on input signals.

Solution

1. Step 1: Understand the role of a decoder

   A decoder takes a small binary input and activates exactly one output line corresponding to that input.

2. Step 2: Compare with other options

   Options A, B, and C describe other components or functions, not a decoder's main role.

3. Final Answer:

   It converts a binary input code into one active output line. -> Option A

4. Quick Check:

   Decoder = binary input to one active output [OK]

Hint: Decoder activates one output from input code [OK]

Common Mistakes:

• Confusing decoder with encoder
• Thinking decoder stores data
• Assuming decoder performs arithmetic

2.

Which of the following is the correct VHDL syntax to declare a 2-to-4 decoder output signal named Y as a 4-bit std_logic_vector?

easy

A. signal Y : std_logic_vector(3 downto 1);

B. signal Y : std_logic_vector(0 downto 3);

C. signal Y : std_logic_vector(3 downto 0);

D. signal Y : std_logic_vector(4 to 1);

Solution

1. Step 1: Understand std_logic_vector indexing

   In VHDL, vectors are often declared with 'downto' for descending indices, so 3 downto 0 means 4 bits indexed 3,2,1,0.

2. Step 2: Check options for correct 4-bit declaration

   signal Y : std_logic_vector(3 downto 0); uses '3 downto 0' which is standard and correct. The other options are incorrect: B '0 downto 3' (invalid direction), C '3 downto 1' (3 bits), D '4 to 1' (invalid direction).

3. Final Answer:

   signal Y : std_logic_vector(3 downto 0); -> Option C

4. Quick Check:

   4-bit vector usually declared as 3 downto 0 [OK]

Hint: Use 'downto' for descending bit order in vectors [OK]

Common Mistakes:

• Using incorrect index ranges
• Confusing 'to' and 'downto' keywords
• Declaring wrong vector size

3.

Given the following VHDL code for a 2-to-4 decoder, what is the output Y when input A = "10"?

process(A)
begin
  case A is
    when "00" => Y <= "0001";
    when "01" => Y <= "0010";
    when "10" => Y <= "0100";
    when "11" => Y <= "1000";
    when others => Y <= "0000";
  end case;
end process;

medium

A. "0100"

B. "0010"

C. "0001"

D. "1000"

Solution

1. Step 1: Match input A with case branches

   The input A is "10", so the case statement matches the third when clause: when "10" => Y <= "0100".

2. Step 2: Confirm output value

   The output Y is assigned "0100" for input "10".

3. Final Answer:

   "0100" -> Option A

4. Quick Check:

   Input "10" activates third output "0100" [OK]

Hint: Match input bits exactly in case statement [OK]

Common Mistakes:

• Mixing up binary input values
• Choosing output for wrong input
• Ignoring 'when others' clause

4.

Identify the error in this VHDL code snippet for a 4-to-2 encoder:

process(I)
begin
  if I = "0001" then Y <= "00";
  elsif I = "0010" then Y <= "01";
  elsif I = "0100" then Y <= "10";
  elsif I = "1000" then Y <= "11";
  else Y <= "00";
end if;
end process;

medium

A. Input I should be declared as std_logic_vector(3 downto 0).

B. The code does not handle multiple active inputs correctly.

C. The process sensitivity list should include Y.

D. The output Y should be declared as std_logic_vector(3 downto 0).

Solution

1. Step 1: Analyze input and output declarations

   Input I is likely a 4-bit vector representing active lines; output Y is 2 bits encoding which input is active.

2. Step 2: Check logic for multiple active inputs

   The code assumes only one input bit is active at a time. It does not handle cases where multiple bits in I are '1', which is invalid for an encoder.

3. Step 3: Review other options

   Input I should be declared as std_logic_vector(3 downto 0). is likely true but not an error in this snippet. The process sensitivity list should include Y. is incorrect; Y should not be in sensitivity list. The output Y should be declared as std_logic_vector(3 downto 0). is wrong because Y is 2 bits, not 4.

4. Final Answer:

   The code does not handle multiple active inputs correctly. -> Option B

5. Quick Check:

   Encoder needs single active input line [OK]

Hint: Encoder requires only one active input line [OK]

Common Mistakes:

• Ignoring multiple active inputs
• Incorrect sensitivity list
• Wrong output size declaration

5.

You need to design a 3-to-8 decoder in VHDL that activates one output line based on a 3-bit input A. Which of the following code snippets correctly implements this decoder?

process(A)
begin
  Y <= (others => '0');
  case A is
    when "000" => Y(0) <= '1';
    when "001" => Y(1) <= '1';
    when "010" => Y(2) <= '1';
    when "011" => Y(3) <= '1';
    when "100" => Y(4) <= '1';
    when "101" => Y(5) <= '1';
    when "110" => Y(6) <= '1';
    when "111" => Y(7) <= '1';
    when others => Y <= (others => '0');
  end case;
end process;

hard

A. The case statement syntax is invalid in VHDL.

B. The code incorrectly sets multiple outputs high simultaneously.

C. The code misses resetting outputs before setting one high.

D. This code correctly sets one output bit high and resets others to zero.

Solution

1. Step 1: Check output initialization

   The line 'Y <= (others => '0');' sets all outputs to zero before activating one output line.

2. Step 2: Verify case statement logic

   Each case sets exactly one bit of Y to '1' based on input A, which is correct for a decoder.

3. Step 3: Confirm syntax correctness

   The case statement and assignments follow proper VHDL syntax.

4. Final Answer:

   This code correctly sets one output bit high and resets others to zero. -> Option D

5. Quick Check:

   Initialize outputs then activate one line [OK]

Hint: Reset outputs before setting one active bit [OK]

Common Mistakes:

• Not resetting outputs before setting one
• Setting multiple outputs high
• Incorrect case statement syntax