Decoder and encoder design in VHDL - Mini Project: Build & Apply

Decoder and Encoder Design in VHDL

📖 Scenario: You are designing simple digital circuits that convert signals from one form to another. A decoder takes a small number of input bits and activates one output line based on the input. An encoder does the opposite: it takes multiple input lines and converts them into a smaller number of output bits.These circuits are used in many electronics devices, like remote controls, keyboards, and communication systems.

🎯 Goal: You will create a 2-to-4 line decoder and a 4-to-2 line encoder using VHDL. You will write the code step-by-step, starting with inputs and outputs, then adding the logic, and finally displaying the output signals.

📋 What You'll Learn

Create a 2-to-4 line decoder entity with inputs input_bits (2 bits) and outputs decoder_out (4 bits).

Create a 4-to-2 line encoder entity with inputs encoder_in (4 bits) and outputs encoded_out (2 bits).

Use simple combinational logic (with when or with-select statements) for both decoder and encoder.

Print or simulate the output signals to verify correct behavior.

💡 Why This Matters

🌍 Real World

Decoders and encoders are basic building blocks in digital electronics used in devices like keyboards, multiplexers, and communication systems to convert signals between different formats.

💼 Career

Understanding how to design and implement decoders and encoders in VHDL is essential for hardware engineers working on FPGA or ASIC design, embedded systems, and digital circuit development.

1

Create the 2-to-4 Decoder Entity and Architecture

Write VHDL code to create an entity called decoder_2to4 with a 2-bit input port named input_bits and a 4-bit output port named decoder_out. Then start the architecture named behavior.

VHDL

-- Your code here to define entity decoder_2to4 and architecture behavior

Need a hint?

Remember to declare the entity with input and output ports exactly as named.

2

Add Decoder Logic Using with-select Statement

Inside the behavior architecture, write a with input_bits select statement to assign decoder_out so that only one bit is '1' corresponding to the binary value of input_bits, and others are '0'. For example, if input_bits is "00", decoder_out should be "0001".

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity decoder_2to4 is
    Port ( input_bits : in STD_LOGIC_VECTOR(1 downto 0);
           decoder_out : out STD_LOGIC_VECTOR(3 downto 0));
end decoder_2to4;

architecture behavior of decoder_2to4 is
begin
-- Add with-select statement for decoder_out here

Need a hint?

Use the with-select statement to assign output patterns for each input.

3

Create the 4-to-2 Encoder Entity and Architecture

Write VHDL code to create an entity called encoder_4to2 with a 4-bit input port named encoder_in and a 2-bit output port named encoded_out. Then start the architecture named behavior.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity decoder_2to4 is
    Port ( input_bits : in STD_LOGIC_VECTOR(1 downto 0);
           decoder_out : out STD_LOGIC_VECTOR(3 downto 0));
end decoder_2to4;

architecture behavior of decoder_2to4 is
begin
    with input_bits select
        decoder_out <= "0001" when "00",
                       "0010" when "01",
                       "0100" when "10",
                       "1000" when "11",
                       "0000" when others;
end behavior;

-- Your code here to define entity encoder_4to2 and architecture behavior

Need a hint?

Define the encoder entity and architecture with the exact port names and sizes.

4

Add Encoder Logic Using with-select Statement and Display Output

Inside the behavior architecture of encoder_4to2, write a with encoder_in select statement to assign encoded_out so that it outputs the binary index of the input bit that is '1'. For example, if encoder_in is "0001", encoded_out should be "00". Then add a process or statement to print the encoded output for the input "0100".

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity decoder_2to4 is
    Port ( input_bits : in STD_LOGIC_VECTOR(1 downto 0);
           decoder_out : out STD_LOGIC_VECTOR(3 downto 0));
end decoder_2to4;

architecture behavior of decoder_2to4 is
begin
    with input_bits select
        decoder_out <= "0001" when "00",
                       "0010" when "01",
                       "0100" when "10",
                       "1000" when "11",
                       "0000" when others;
end behavior;

entity encoder_4to2 is
    Port ( encoder_in : in STD_LOGIC_VECTOR(3 downto 0);
           encoded_out : out STD_LOGIC_VECTOR(1 downto 0));
end encoder_4to2;

architecture behavior of encoder_4to2 is
begin
-- Add with-select statement for encoded_out here

-- Add a simple process to print encoded_out for input "0100"

Need a hint?

Use with-select to assign encoded_out. Use a process with write and writeline to print the output.