Decoder and encoder design in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of 2-to-4 Decoder VHDL Code

What is the output vector Y when the input A is "10" in this 2-to-4 decoder?

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity decoder_2to4 is
    Port ( A : in STD_LOGIC_VECTOR (1 downto 0);
           Y : out STD_LOGIC_VECTOR (3 downto 0));
end decoder_2to4;

architecture Behavioral of decoder_2to4 is
begin
    process(A)
    begin
        case A is
            when "00" => Y <= "0001";
            when "01" => Y <= "0010";
            when "10" => Y <= "0100";
            when "11" => Y <= "1000";
            when others => Y <= "0000";
        end case;
    end process;
end Behavioral;

A "0001"

B "1000"

C "0100"

D "0010"

💡 Hint

Check the case statement for input "10".

The decoder sets the output bit corresponding to the binary input index. For input "10" (decimal 2), the third bit (index 2) is set to '1', which is "0100".

❓ Predict Output

intermediate

Output of 4-to-2 Encoder VHDL Code

What is the output vector Y when the input D is "0100" in this 4-to-2 encoder?

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity encoder_4to2 is
    Port ( D : in STD_LOGIC_VECTOR (3 downto 0);
           Y : out STD_LOGIC_VECTOR (1 downto 0));
end encoder_4to2;

architecture Behavioral of encoder_4to2 is
begin
    process(D)
    begin
        case D is
            when "0001" => Y <= "00";
            when "0010" => Y <= "01";
            when "0100" => Y <= "10";
            when "1000" => Y <= "11";
            when others => Y <= "00";
        end case;
    end process;
end Behavioral;

A "00"

B "01"

C "11"

D "10"

💡 Hint

Look at the case for input "0100".

The encoder outputs the binary index of the input bit set to '1'. For input "0100", the bit at index 2 is set, so output is "10".

🔧 Debug

advanced

Identify the Error in 3-to-8 Decoder VHDL Code

What error will this VHDL code produce when compiled?

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity decoder_3to8 is
    Port ( A : in STD_LOGIC_VECTOR (2 downto 0);
           Y : out STD_LOGIC_VECTOR (7 downto 0));
end decoder_3to8;

architecture Behavioral of decoder_3to8 is
begin
    process(A)
    begin
        case A is
            when "000" => Y <= "00000001";
            when "001" => Y <= "00000010";
            when "010" => Y <= "00000100";
            when "011" => Y <= "00001000";
            when "100" => Y <= "00010000";
            when "101" => Y <= "00100000";
            when "110" => Y <= "01000000";
            when "111" => Y <= "10000000";
            when others => Y <= "00000000";
        end case;
    end process;
end Behavioral;

A Syntax error: missing semicolon after 'when others' assignment

B Runtime error: index out of range

C No error, code compiles and runs correctly

D Type error: incompatible assignment to Y

💡 Hint

Check the syntax of the case statement carefully.

The 'when others' assignment line is missing a semicolon at the end, causing a syntax error during compilation.

🧠 Conceptual

advanced

Behavior of Priority Encoder with Multiple Inputs High

In a 4-to-2 priority encoder, if inputs D3=1, D2=1, D1=0, D0=1, which output will the encoder produce?

A Output corresponds to D3 ("11") because it has highest priority

B Output corresponds to D2 ("10") because it is the first detected

C Output corresponds to D0 ("00") because it is the lowest index

D Output is undefined due to multiple inputs high

💡 Hint

Priority encoder outputs the highest priority input index.

Priority encoders output the binary code of the highest priority input that is high. Here, D3 has the highest priority, so output is "11".

🚀 Application

expert

Design Output of a 3-to-8 Decoder with Enable Signal

Given this VHDL code for a 3-to-8 decoder with an enable input, what is the output Y when A = "101" and EN = '0'?

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity decoder_3to8_en is
    Port ( A : in STD_LOGIC_VECTOR (2 downto 0);
           EN : in STD_LOGIC;
           Y : out STD_LOGIC_VECTOR (7 downto 0));
end decoder_3to8_en;

architecture Behavioral of decoder_3to8_en is
begin
    process(A, EN)
    begin
        if EN = '1' then
            case A is
                when "000" => Y <= "00000001";
                when "001" => Y <= "00000010";
                when "010" => Y <= "00000100";
                when "011" => Y <= "00001000";
                when "100" => Y <= "00010000";
                when "101" => Y <= "00100000";
                when "110" => Y <= "01000000";
                when "111" => Y <= "10000000";
                when others => Y <= "00000000";
            end case;
        else
            Y <= "00000000";
        end if;
    end process;
end Behavioral;

A "00100000"

B "00000000"

C "10000000"

D "00010000"

💡 Hint

Check the enable signal condition.

When EN = '0', the output Y is forced to all zeros regardless of input A.

Practice

1.

What is the main function of a decoder in VHDL?

easy

A. It converts a binary input code into one active output line.

B. It compresses multiple output lines into a smaller input code.

C. It stores data temporarily in registers.

D. It performs arithmetic operations on input signals.

Solution

1. Step 1: Understand the role of a decoder

   A decoder takes a small binary input and activates exactly one output line corresponding to that input.

2. Step 2: Compare with other options

   Options A, B, and C describe other components or functions, not a decoder's main role.

3. Final Answer:

   It converts a binary input code into one active output line. -> Option A

4. Quick Check:

   Decoder = binary input to one active output [OK]

Hint: Decoder activates one output from input code [OK]

Common Mistakes:

• Confusing decoder with encoder
• Thinking decoder stores data
• Assuming decoder performs arithmetic

2.

Which of the following is the correct VHDL syntax to declare a 2-to-4 decoder output signal named Y as a 4-bit std_logic_vector?

easy

A. signal Y : std_logic_vector(3 downto 1);

B. signal Y : std_logic_vector(0 downto 3);

C. signal Y : std_logic_vector(3 downto 0);

D. signal Y : std_logic_vector(4 to 1);

Solution

1. Step 1: Understand std_logic_vector indexing

   In VHDL, vectors are often declared with 'downto' for descending indices, so 3 downto 0 means 4 bits indexed 3,2,1,0.

2. Step 2: Check options for correct 4-bit declaration

   signal Y : std_logic_vector(3 downto 0); uses '3 downto 0' which is standard and correct. The other options are incorrect: B '0 downto 3' (invalid direction), C '3 downto 1' (3 bits), D '4 to 1' (invalid direction).

3. Final Answer:

   signal Y : std_logic_vector(3 downto 0); -> Option C

4. Quick Check:

   4-bit vector usually declared as 3 downto 0 [OK]

Hint: Use 'downto' for descending bit order in vectors [OK]

Common Mistakes:

• Using incorrect index ranges
• Confusing 'to' and 'downto' keywords
• Declaring wrong vector size

3.

Given the following VHDL code for a 2-to-4 decoder, what is the output Y when input A = "10"?

process(A)
begin
  case A is
    when "00" => Y <= "0001";
    when "01" => Y <= "0010";
    when "10" => Y <= "0100";
    when "11" => Y <= "1000";
    when others => Y <= "0000";
  end case;
end process;

medium

A. "0100"

B. "0010"

C. "0001"

D. "1000"

Solution

1. Step 1: Match input A with case branches

   The input A is "10", so the case statement matches the third when clause: when "10" => Y <= "0100".

2. Step 2: Confirm output value

   The output Y is assigned "0100" for input "10".

3. Final Answer:

   "0100" -> Option A

4. Quick Check:

   Input "10" activates third output "0100" [OK]

Hint: Match input bits exactly in case statement [OK]

Common Mistakes:

• Mixing up binary input values
• Choosing output for wrong input
• Ignoring 'when others' clause

4.

Identify the error in this VHDL code snippet for a 4-to-2 encoder:

process(I)
begin
  if I = "0001" then Y <= "00";
  elsif I = "0010" then Y <= "01";
  elsif I = "0100" then Y <= "10";
  elsif I = "1000" then Y <= "11";
  else Y <= "00";
end if;
end process;

medium

A. Input I should be declared as std_logic_vector(3 downto 0).

B. The code does not handle multiple active inputs correctly.

C. The process sensitivity list should include Y.

D. The output Y should be declared as std_logic_vector(3 downto 0).

Solution

1. Step 1: Analyze input and output declarations

   Input I is likely a 4-bit vector representing active lines; output Y is 2 bits encoding which input is active.

2. Step 2: Check logic for multiple active inputs

   The code assumes only one input bit is active at a time. It does not handle cases where multiple bits in I are '1', which is invalid for an encoder.

3. Step 3: Review other options

   Input I should be declared as std_logic_vector(3 downto 0). is likely true but not an error in this snippet. The process sensitivity list should include Y. is incorrect; Y should not be in sensitivity list. The output Y should be declared as std_logic_vector(3 downto 0). is wrong because Y is 2 bits, not 4.

4. Final Answer:

   The code does not handle multiple active inputs correctly. -> Option B

5. Quick Check:

   Encoder needs single active input line [OK]

Hint: Encoder requires only one active input line [OK]

Common Mistakes:

• Ignoring multiple active inputs
• Incorrect sensitivity list
• Wrong output size declaration

5.

You need to design a 3-to-8 decoder in VHDL that activates one output line based on a 3-bit input A. Which of the following code snippets correctly implements this decoder?

process(A)
begin
  Y <= (others => '0');
  case A is
    when "000" => Y(0) <= '1';
    when "001" => Y(1) <= '1';
    when "010" => Y(2) <= '1';
    when "011" => Y(3) <= '1';
    when "100" => Y(4) <= '1';
    when "101" => Y(5) <= '1';
    when "110" => Y(6) <= '1';
    when "111" => Y(7) <= '1';
    when others => Y <= (others => '0');
  end case;
end process;

hard

A. The case statement syntax is invalid in VHDL.

B. The code incorrectly sets multiple outputs high simultaneously.

C. The code misses resetting outputs before setting one high.

D. This code correctly sets one output bit high and resets others to zero.

Solution

1. Step 1: Check output initialization

   The line 'Y <= (others => '0');' sets all outputs to zero before activating one output line.

2. Step 2: Verify case statement logic

   Each case sets exactly one bit of Y to '1' based on input A, which is correct for a decoder.

3. Step 3: Confirm syntax correctness

   The case statement and assignments follow proper VHDL syntax.

4. Final Answer:

   This code correctly sets one output bit high and resets others to zero. -> Option D

5. Quick Check:

   Initialize outputs then activate one line [OK]

Hint: Reset outputs before setting one active bit [OK]

Common Mistakes:

• Not resetting outputs before setting one
• Setting multiple outputs high
• Incorrect case statement syntax