Decoder and encoder design in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of 2-to-4 Decoder VHDL Code

What is the output vector Y when the input A is "10" in this 2-to-4 decoder?

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity decoder_2to4 is
    Port ( A : in STD_LOGIC_VECTOR (1 downto 0);
           Y : out STD_LOGIC_VECTOR (3 downto 0));
end decoder_2to4;

architecture Behavioral of decoder_2to4 is
begin
    process(A)
    begin
        case A is
            when "00" => Y <= "0001";
            when "01" => Y <= "0010";
            when "10" => Y <= "0100";
            when "11" => Y <= "1000";
            when others => Y <= "0000";
        end case;
    end process;
end Behavioral;

A "0001"

B "1000"

C "0100"

D "0010"

💡 Hint

Check the case statement for input "10".

The decoder sets the output bit corresponding to the binary input index. For input "10" (decimal 2), the third bit (index 2) is set to '1', which is "0100".

❓ Predict Output

intermediate

Output of 4-to-2 Encoder VHDL Code

What is the output vector Y when the input D is "0100" in this 4-to-2 encoder?

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity encoder_4to2 is
    Port ( D : in STD_LOGIC_VECTOR (3 downto 0);
           Y : out STD_LOGIC_VECTOR (1 downto 0));
end encoder_4to2;

architecture Behavioral of encoder_4to2 is
begin
    process(D)
    begin
        case D is
            when "0001" => Y <= "00";
            when "0010" => Y <= "01";
            when "0100" => Y <= "10";
            when "1000" => Y <= "11";
            when others => Y <= "00";
        end case;
    end process;
end Behavioral;

A "00"

B "01"

C "11"

D "10"

💡 Hint

Look at the case for input "0100".

The encoder outputs the binary index of the input bit set to '1'. For input "0100", the bit at index 2 is set, so output is "10".

🔧 Debug

advanced

Identify the Error in 3-to-8 Decoder VHDL Code

What error will this VHDL code produce when compiled?

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity decoder_3to8 is
    Port ( A : in STD_LOGIC_VECTOR (2 downto 0);
           Y : out STD_LOGIC_VECTOR (7 downto 0));
end decoder_3to8;

architecture Behavioral of decoder_3to8 is
begin
    process(A)
    begin
        case A is
            when "000" => Y <= "00000001";
            when "001" => Y <= "00000010";
            when "010" => Y <= "00000100";
            when "011" => Y <= "00001000";
            when "100" => Y <= "00010000";
            when "101" => Y <= "00100000";
            when "110" => Y <= "01000000";
            when "111" => Y <= "10000000";
            when others => Y <= "00000000";
        end case;
    end process;
end Behavioral;

A Syntax error: missing semicolon after 'when others' assignment

B Runtime error: index out of range

C No error, code compiles and runs correctly

D Type error: incompatible assignment to Y

💡 Hint

Check the syntax of the case statement carefully.

The 'when others' assignment line is missing a semicolon at the end, causing a syntax error during compilation.

🧠 Conceptual

advanced

Behavior of Priority Encoder with Multiple Inputs High

In a 4-to-2 priority encoder, if inputs D3=1, D2=1, D1=0, D0=1, which output will the encoder produce?

A Output corresponds to D3 ("11") because it has highest priority

B Output corresponds to D2 ("10") because it is the first detected

C Output corresponds to D0 ("00") because it is the lowest index

D Output is undefined due to multiple inputs high

💡 Hint

Priority encoder outputs the highest priority input index.

Priority encoders output the binary code of the highest priority input that is high. Here, D3 has the highest priority, so output is "11".

🚀 Application

expert

Design Output of a 3-to-8 Decoder with Enable Signal

Given this VHDL code for a 3-to-8 decoder with an enable input, what is the output Y when A = "101" and EN = '0'?

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity decoder_3to8_en is
    Port ( A : in STD_LOGIC_VECTOR (2 downto 0);
           EN : in STD_LOGIC;
           Y : out STD_LOGIC_VECTOR (7 downto 0));
end decoder_3to8_en;

architecture Behavioral of decoder_3to8_en is
begin
    process(A, EN)
    begin
        if EN = '1' then
            case A is
                when "000" => Y <= "00000001";
                when "001" => Y <= "00000010";
                when "010" => Y <= "00000100";
                when "011" => Y <= "00001000";
                when "100" => Y <= "00010000";
                when "101" => Y <= "00100000";
                when "110" => Y <= "01000000";
                when "111" => Y <= "10000000";
                when others => Y <= "00000000";
            end case;
        else
            Y <= "00000000";
        end if;
    end process;
end Behavioral;

A "00100000"

B "00000000"

C "10000000"

D "00010000"

💡 Hint

Check the enable signal condition.

When EN = '0', the output Y is forced to all zeros regardless of input A.