Component instantiation in testbench in VHDL - Step-by-Step Execution

Concept Flow - Component instantiation in testbench

Declare component in testbench

↓

Map signals to component ports

↓

Instantiate component with port map

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Run simulation to test component behavior

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Observe outputs and verify correctness

This flow shows how a component is declared, connected, instantiated in a testbench, and then simulated to check its behavior.

Execution Sample

VHDL

component AND_GATE is
  port(a, b: in std_logic; y: out std_logic);
end component;

-- Instantiate in testbench
UUT: AND_GATE port map(a => tb_a, b => tb_b, y => tb_y);

This code declares an AND_GATE component and instantiates it in a testbench, connecting test signals to its ports.

Execution Table

Step	Action	Signal/Component	Value/State	Notes
1	Declare component	AND_GATE	Defined with ports a,b,y	Component interface ready
2	Declare testbench signals	tb_a, tb_b, tb_y	Initialized to '0'	Signals to connect to component
3	Instantiate component	UUT	Ports mapped: a=>tb_a, b=>tb_b, y=>tb_y	Component linked to testbench signals
4	Apply inputs	tb_a, tb_b	tb_a='1', tb_b='0'	Stimulus applied to inputs
5	Simulate component	UUT output y	tb_y='0'	AND gate output for inputs 1 and 0
6	Apply inputs	tb_a, tb_b	tb_a='1', tb_b='1'	Change inputs to both 1
7	Simulate component	UUT output y	tb_y='1'	AND gate output for inputs 1 and 1
8	End simulation	-	-	Testbench run complete

💡 Simulation ends after all input combinations tested and outputs observed

Variable Tracker

Signal	Start	After Step 4	After Step 6	Final
tb_a	'0'	'1'	'1'	'1'
tb_b	'0'	'0'	'1'	'1'
tb_y	'0'	'0'	'1'	'1'

Key Moments - 3 Insights

Why do we declare the component inside the testbench before instantiating it?

Declaring the component defines its interface so the testbench knows the ports to connect. See execution_table step 1 where the component is declared before instantiation at step 3.

How do signals in the testbench connect to the component ports?

Signals are mapped to ports using port map syntax during instantiation (step 3). This links testbench signals to the component's inputs and outputs.

Why do we change input signals and observe outputs in steps 4-7?

Changing inputs and observing outputs simulates how the component behaves with different inputs, verifying its correctness as shown in execution_table steps 4-7.

Visual Quiz - 3 Questions

Look at the execution_table, what is the value of tb_y after step 5?

A '0'

B '1'

C 'X' (unknown)

D 'Z' (high impedance)

💡 Hint

Check the row for step 5 in execution_table where inputs are tb_a='1' and tb_b='0'.

At which step does the component output tb_y become '1'?

A Step 5

B Step 7

C Step 4

D Step 8

💡 Hint

Look at execution_table rows for steps 5 and 7 to see output changes.

If tb_b was never changed from '0', what would tb_y be after step 7?

A 'X'

B '1'

C '0'

D 'Z'

💡 Hint

Refer to variable_tracker and execution_table steps 4 and 5 for output when tb_b='0'.

Concept Snapshot

Component instantiation in testbench:
- Declare component with ports
- Declare testbench signals
- Instantiate component with port map
- Apply input signals
- Simulate and observe outputs
- Verify behavior matches expectations

Full Transcript

In VHDL testbenches, you first declare the component you want to test, specifying its input and output ports. Then, you declare signals in the testbench to connect to these ports. Next, you instantiate the component inside the testbench using a port map to link signals to ports. During simulation, you change input signals and observe the output signals to verify the component's behavior. This process helps ensure the component works correctly before using it in a larger design.