Component instantiation in testbench in VHDL - Mini Project: Build & Apply

Component instantiation in testbench

📖 Scenario: You are designing a simple digital circuit in VHDL and want to test it using a testbench. The testbench will create an instance of your component and apply some test signals to check its behavior.

🎯 Goal: Create a VHDL testbench that instantiates a component called and_gate with two inputs and one output. You will set up the signals, instantiate the component, and then print the output values during simulation.

📋 What You'll Learn

Create signals for inputs and output with exact names: a, b, and y

Declare a component called and_gate with ports a, b, and y

Instantiate the component inside the testbench architecture using the exact instance name uut

Assign values to inputs a and b and observe the output y

Print the output y using report statements

💡 Why This Matters

🌍 Real World

Testbenches are used in digital design to verify that components work correctly before building physical hardware.

💼 Career

Understanding component instantiation and testbenches is essential for FPGA and ASIC design engineers to validate their designs.

1

Create signals for inputs and output

Create signals called a, b, and y of type std_logic inside the testbench architecture.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity tb_and_gate is
end tb_and_gate;

architecture behavior of tb_and_gate is
    -- Create signals a, b, and y of type std_logic
    -- Your code here
begin
end behavior;

Need a hint?

Signals are declared inside the architecture before the begin keyword.

2

Declare the component and_gate

Inside the testbench architecture, declare a component called and_gate with ports a and b as inputs of type std_logic, and y as output of type std_logic.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity tb_and_gate is
end tb_and_gate;

architecture behavior of tb_and_gate is
    signal a : std_logic := '0';
    signal b : std_logic := '0';
    signal y : std_logic;

    -- Declare component and_gate with ports a, b, y
    -- Your code here
begin
end behavior;

Need a hint?

Use the component keyword and declare ports with directions in or out.

3

Instantiate the component and assign signals

Instantiate the component and_gate inside the architecture body with instance name uut. Connect the ports a, b, and y to the signals with the same names using port map.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity tb_and_gate is
end tb_and_gate;

architecture behavior of tb_and_gate is
    signal a : std_logic := '0';
    signal b : std_logic := '0';
    signal y : std_logic;

    component and_gate is
        port(
            a : in std_logic;
            b : in std_logic;
            y : out std_logic
        );
    end component;

begin
    -- Instantiate and_gate with instance name uut and connect ports
    -- Your code here
end behavior;

Need a hint?

Use the instance name uut and connect ports with port map.

4

Assign input values and print output

Inside the architecture body, create a process that assigns a = '1' and b = '0', then waits for 10 ns. Use report statements to print the value of y as a string.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity tb_and_gate is
end tb_and_gate;

architecture behavior of tb_and_gate is
    signal a : std_logic := '0';
    signal b : std_logic := '0';
    signal y : std_logic;

    component and_gate is
        port(
            a : in std_logic;
            b : in std_logic;
            y : out std_logic
        );
    end component;

begin
    uut : and_gate port map(
        a => a,
        b => b,
        y => y
    );

    -- Create a process to assign inputs and report output
    -- Your code here
end behavior;

Need a hint?

Use a process with signal assignments, wait for 10 ns;, and report to print the output.