Component instantiation in testbench in VHDL - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to instantiate the component named 'my_component' in the testbench.

VHDL

uut: entity work.my_component port map([1]);

Drag options to blanks, or click blank then click option'

Aclk => clk rst => rst

Bclk, rst

Cclk => clk, rst => rst

Dclk => rst, rst => clk

Attempts:

3 left

💡 Hint

Common Mistakes

Forgetting the => operator in port mapping.

Not separating port mappings with commas.

The correct syntax for port mapping uses the => operator to connect signals by name.

2fill in blank

medium

Complete the code to declare the component 'my_component' in the testbench architecture.

VHDL

component my_component is
  port(
    clk : in std_logic;
    rst : in std_logic
  );
end component;

signal clk : std_logic := '0';
signal rst : std_logic := '1';

begin
  [1]
end;

Drag options to blanks, or click blank then click option'

Auut: my_component port map(clk => clk, rst => rst);

Buut: entity work.my_component port map(clk, rst);

Cuut: my_component port map(clk, rst);

Duut: entity my_component port map(clk => clk, rst => rst);

Attempts:

3 left

💡 Hint

Common Mistakes

Using entity keyword incorrectly in component instantiation.

Using positional port mapping without parentheses.

The component instantiation must use the component name and port map with named associations.

3fill in blank

hard

Fix the error in the component instantiation by completing the port map correctly.

VHDL

uut: entity work.my_component port map(clk => [1], rst => rst);

Drag options to blanks, or click blank then click option'

Arst

B'1'

C'0'

Dclk

Attempts:

3 left

💡 Hint

Common Mistakes

Connecting clk port to a constant like '1' or '0'.

Swapping clk and rst signals.

The signal 'clk' must be connected to the clk port, not a constant or other signal.

4fill in blank

hard

Fill both blanks to complete the component instantiation with correct port mapping and label.

VHDL

[1]: entity work.my_component port map([2]);

Drag options to blanks, or click blank then click option'

Auut

Bclk => clk, rst => rst

Cclk, rst

Dmy_component

Attempts:

3 left

💡 Hint

Common Mistakes

Using positional port mapping without parentheses.

Omitting the instance label.

The label 'uut' is commonly used for the unit under test, and port mapping requires named associations.

5fill in blank

hard

Fill all three blanks to instantiate 'my_component' with label, entity, and port map correctly.

VHDL

[1]: entity [2] port map([3]);

Drag options to blanks, or click blank then click option'

Ainst1

Bwork.my_component

Cclk => clk, rst => rst

Dmy_component

Attempts:

3 left

💡 Hint

Common Mistakes

Using incorrect entity name without library prefix.

Using positional port mapping instead of named.

The instance label is 'inst1', the entity is 'work.my_component', and the port map uses named associations.