Component instantiation in testbench in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of a simple component instantiation in a testbench

Consider the following VHDL testbench code that instantiates a component. What will be the output on the signal out_signal after 10 ns?

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity tb is
end tb;

architecture behavior of tb is
  signal in_signal : std_logic := '0';
  signal out_signal : std_logic;

  component inverter is
    port(
      a : in std_logic;
      y : out std_logic
    );
  end component;

begin
  uut: inverter port map(a => in_signal, y => out_signal);

  process
  begin
    in_signal <= '0';
    wait for 5 ns;
    in_signal <= '1';
    wait for 5 ns;
    wait;
  end process;
end behavior;

A out_signal = '1' at 10 ns

B out_signal = '0' at 10 ns

C out_signal toggles between '0' and '1' every 5 ns

D out_signal remains undefined (U) at 10 ns

💡 Hint

Think about what an inverter does to the input signal.

The component inverter outputs the logical NOT of the input a. At 10 ns, in_signal is '1', so out_signal will be NOT '1', which is '0'.

❓ Predict Output

intermediate

Signal value after component instantiation with delayed input

Given the following testbench snippet, what is the value of out_signal at 15 ns?

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity tb is
end tb;

architecture behavior of tb is
  signal in_signal : std_logic := '0';
  signal out_signal : std_logic;

  component buffer is
    port(
      a : in std_logic;
      y : out std_logic
    );
  end component;

begin
  uut: buffer port map(a => in_signal, y => out_signal);

  process
  begin
    in_signal <= '0';
    wait for 10 ns;
    in_signal <= '1';
    wait for 10 ns;
    wait;
  end process;
end behavior;

A out_signal = 'U' (undefined) at 15 ns

B out_signal = '0' at 15 ns

C out_signal = '1' at 15 ns

D out_signal toggles every 5 ns

💡 Hint

Remember that signal assignments take effect after the delta cycle or delay.

At 10 ns, in_signal is assigned '1'. The buffer outputs the input value directly (after delta cycle), so by 15 ns, out_signal is '1'.

🔧 Debug

advanced

Identify the error in component instantiation

Examine the following testbench code snippet. What error will occur when compiling or simulating?

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity tb is
end tb;

architecture behavior of tb is
  signal in_signal : std_logic := '0';
  signal out_signal : std_logic;

  component and_gate is
    port(
      a : in std_logic;
      b : in std_logic;
      y : out std_logic
    );
  end component;

begin
  uut: and_gate port map(a => in_signal, y => out_signal);

  process
  begin
    in_signal <= '1';
    wait;
  end process;
end behavior;

A Compilation error: missing port 'b' in port map

B Runtime error: signal 'b' is undefined

C Simulation runs but output is always '0'

D No error, simulation runs correctly

💡 Hint

Check if all ports of the component are connected in the port map.

The component and_gate has three ports: a, b, and y. The port map only connects a and y. Missing b causes a compilation error.

📝 Syntax

advanced

Syntax error in component instantiation

Which option contains a syntax error in the component instantiation within a testbench?

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity tb is
end tb;

architecture behavior of tb is
  signal in_signal : std_logic := '0';
  signal out_signal : std_logic;

  component not_gate is
    port(
      a : in std_logic;
      y : out std_logic
    );
  end component;

begin
  -- component instantiation here
end behavior;

A uut: not_gate port map(a => in_signal y => out_signal);

B ;)langis_tuo >= y ,langis_ni >= a(pam trop etag_ton :tuu

C uut: not_gate port map(a => in_signal, y => out_signal);

D ut: not_gate port map(a => in_signal, y => out_signal);

💡 Hint

Look carefully at the punctuation between port mappings.

Option A is missing a comma between a => in_signal and y => out_signal, causing a syntax error.

🚀 Application

expert

Number of component instances in a testbench

In the following testbench code, how many instances of the component flip_flop are created?

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity tb is
end tb;

architecture behavior of tb is
  signal d, clk, q1, q2 : std_logic := '0';

  component flip_flop is
    port(
      d : in std_logic;
      clk : in std_logic;
      q : out std_logic
    );
  end component;

begin
  ff1: flip_flop port map(d => d, clk => clk, q => q1);
  ff2: flip_flop port map(d => q1, clk => clk, q => q2);
  ff3: flip_flop port map(d => q2, clk => clk, q => open);
end behavior;

A 0

B 2

C 1

D 3

💡 Hint

Count each unique label that instantiates the component.

There are three component instances: ff1, ff2, and ff3. Each is a separate instantiation of flip_flop.