Component instantiation in testbench in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of a simple component instantiation in a testbench

Consider the following VHDL testbench code that instantiates a component. What will be the output on the signal out_signal after 10 ns?

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity tb is
end tb;

architecture behavior of tb is
  signal in_signal : std_logic := '0';
  signal out_signal : std_logic;

  component inverter is
    port(
      a : in std_logic;
      y : out std_logic
    );
  end component;

begin
  uut: inverter port map(a => in_signal, y => out_signal);

  process
  begin
    in_signal <= '0';
    wait for 5 ns;
    in_signal <= '1';
    wait for 5 ns;
    wait;
  end process;
end behavior;

A out_signal = '1' at 10 ns

B out_signal = '0' at 10 ns

C out_signal toggles between '0' and '1' every 5 ns

D out_signal remains undefined (U) at 10 ns

💡 Hint

Think about what an inverter does to the input signal.

The component inverter outputs the logical NOT of the input a. At 10 ns, in_signal is '1', so out_signal will be NOT '1', which is '0'.

❓ Predict Output

intermediate

Signal value after component instantiation with delayed input

Given the following testbench snippet, what is the value of out_signal at 15 ns?

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity tb is
end tb;

architecture behavior of tb is
  signal in_signal : std_logic := '0';
  signal out_signal : std_logic;

  component buffer is
    port(
      a : in std_logic;
      y : out std_logic
    );
  end component;

begin
  uut: buffer port map(a => in_signal, y => out_signal);

  process
  begin
    in_signal <= '0';
    wait for 10 ns;
    in_signal <= '1';
    wait for 10 ns;
    wait;
  end process;
end behavior;

A out_signal = 'U' (undefined) at 15 ns

B out_signal = '0' at 15 ns

C out_signal = '1' at 15 ns

D out_signal toggles every 5 ns

💡 Hint

Remember that signal assignments take effect after the delta cycle or delay.

At 10 ns, in_signal is assigned '1'. The buffer outputs the input value directly (after delta cycle), so by 15 ns, out_signal is '1'.

🔧 Debug

advanced

Identify the error in component instantiation

Examine the following testbench code snippet. What error will occur when compiling or simulating?

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity tb is
end tb;

architecture behavior of tb is
  signal in_signal : std_logic := '0';
  signal out_signal : std_logic;

  component and_gate is
    port(
      a : in std_logic;
      b : in std_logic;
      y : out std_logic
    );
  end component;

begin
  uut: and_gate port map(a => in_signal, y => out_signal);

  process
  begin
    in_signal <= '1';
    wait;
  end process;
end behavior;

A Compilation error: missing port 'b' in port map

B Runtime error: signal 'b' is undefined

C Simulation runs but output is always '0'

D No error, simulation runs correctly

💡 Hint

Check if all ports of the component are connected in the port map.

The component and_gate has three ports: a, b, and y. The port map only connects a and y. Missing b causes a compilation error.

📝 Syntax

advanced

Syntax error in component instantiation

Which option contains a syntax error in the component instantiation within a testbench?

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity tb is
end tb;

architecture behavior of tb is
  signal in_signal : std_logic := '0';
  signal out_signal : std_logic;

  component not_gate is
    port(
      a : in std_logic;
      y : out std_logic
    );
  end component;

begin
  -- component instantiation here
end behavior;

A uut: not_gate port map(a => in_signal y => out_signal);

B ;)langis_tuo >= y ,langis_ni >= a(pam trop etag_ton :tuu

C uut: not_gate port map(a => in_signal, y => out_signal);

D ut: not_gate port map(a => in_signal, y => out_signal);

💡 Hint

Look carefully at the punctuation between port mappings.

Option A is missing a comma between a => in_signal and y => out_signal, causing a syntax error.

🚀 Application

expert

Number of component instances in a testbench

In the following testbench code, how many instances of the component flip_flop are created?

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity tb is
end tb;

architecture behavior of tb is
  signal d, clk, q1, q2 : std_logic := '0';

  component flip_flop is
    port(
      d : in std_logic;
      clk : in std_logic;
      q : out std_logic
    );
  end component;

begin
  ff1: flip_flop port map(d => d, clk => clk, q => q1);
  ff2: flip_flop port map(d => q1, clk => clk, q => q2);
  ff3: flip_flop port map(d => q2, clk => clk, q => open);
end behavior;

A 0

B 2

C 1

D 3

💡 Hint

Count each unique label that instantiates the component.

There are three component instances: ff1, ff2, and ff3. Each is a separate instantiation of flip_flop.

Practice

1. What is the main purpose of component instantiation in a VHDL testbench?

easy

A. To write comments for the testbench

B. To include and test a design unit inside the testbench

C. To declare new signals in the testbench

D. To define the clock period

Solution

1. Step 1: Understand component instantiation role

   Component instantiation allows you to use a design module inside another design or testbench.

2. Step 2: Identify testbench purpose

   In a testbench, you instantiate the design to apply test signals and observe outputs.

3. Final Answer:

   To include and test a design unit inside the testbench -> Option B

4. Quick Check:

   Component instantiation = test design inside testbench [OK]

Hint: Component instantiation means using design parts inside testbench [OK]

Common Mistakes:

• Confusing instantiation with signal declaration
• Thinking it defines clock or timing
• Assuming it is for comments only

2. Which of the following is the correct syntax to instantiate a component named my_component with ports clk and rst in a testbench?

easy

A. U1: my_component(clk => clk, rst => rst);

B. my_component U1(clk, rst);

C. U1: my_component port map(clk => clk, rst => rst);

D. component my_component(clk, rst);

Solution

1. Step 1: Recall component instantiation syntax

   The correct syntax uses an instance label, colon, component name, and port map with named associations.

2. Step 2: Match syntax to options

   U1: my_component port map(clk => clk, rst => rst); matches the correct syntax: instance label 'U1:', component name, and port map with named ports.

3. Final Answer:

   U1: my_component port map(clk => clk, rst => rst); -> Option C

4. Quick Check:

   Instance label + component + port map = correct syntax [OK]

Hint: Use instance_label: component_name port map(...) [OK]

Common Mistakes:

• Omitting 'port map' keyword
• Using component declaration syntax instead of instantiation
• Placing ports without '=>' named association

3. Given the following VHDL testbench snippet:

signal clk_tb : std_logic := '0';
signal rst_tb : std_logic := '1';

U1: my_component port map(clk => clk_tb, rst => rst_tb);

What is the role of clk_tb and rst_tb in this instantiation?

medium

A. They are variables declared inside the component

B. They are component names

C. They are constants used for timing

D. They are internal signals connected to the component's ports

Solution

1. Step 1: Identify signals in testbench

   Signals clk_tb and rst_tb are declared in the testbench and initialized.

2. Step 2: Understand port mapping

   In the port map, these signals connect to the component's ports clk and rst, providing inputs or outputs.

3. Final Answer:

   They are internal signals connected to the component's ports -> Option D

4. Quick Check:

   Testbench signals connect to component ports [OK]

Hint: Signals in port map connect testbench to component ports [OK]

Common Mistakes:

• Confusing signals with component names
• Thinking signals are constants or variables inside component
• Ignoring signal initialization

4. Identify the error in this component instantiation inside a testbench:

U1 my_component port map(clk => clk_tb, rst => rst_tb);

medium

A. Missing colon after instance label

B. Incorrect port names used

C. Signals not declared

D. Missing semicolon at end

Solution

1. Step 1: Check instance label syntax

   The instance label must be followed by a colon ':' before the component name.

2. Step 2: Analyze given code

   The code has 'U1 my_component' without colon, which is a syntax error.

3. Final Answer:

   Missing colon after instance label -> Option A

4. Quick Check:

   Instance label must end with ':' [OK]

Hint: Instance label must have colon ':' after it [OK]

Common Mistakes:

• Omitting colon after instance label
• Confusing port map syntax
• Forgetting semicolon at end

5. You want to instantiate two copies of a component my_component in your testbench with different signals. Which is the correct way to do this?

hard

A. U1: my_component port map(clk => clk1, rst => rst1); U2: my_component port map(clk => clk2, rst => rst2);

B. my_component U1(clk1, rst1); my_component U2(clk2, rst2);

C. component my_component port map(clk => clk1, rst => rst1); component my_component port map(clk => clk2, rst => rst2);

D. U1: my_component(clk1, rst1); U2: my_component(clk2, rst2);

Solution

1. Step 1: Understand multiple instantiations

   Each instance must have a unique label and use port map with named associations.

2. Step 2: Check options for correct syntax

   U1: my_component port map(clk => clk1, rst => rst1); U2: my_component port map(clk => clk2, rst => rst2); correctly uses unique labels U1 and U2, component name, and port map with named ports.

3. Final Answer:

   U1: my_component port map(clk => clk1, rst => rst1); U2: my_component port map(clk => clk2, rst => rst2); -> Option A

4. Quick Check:

   Multiple instances need unique labels and port maps [OK]

Hint: Use unique labels and port map for each instance [OK]

Common Mistakes:

• Using same instance label twice
• Omitting port map keyword
• Using component declaration instead of instantiation