ALU design in VHDL - Step-by-Step Execution

Concept Flow - ALU design

Input A, Input B, Control Signals

↓

Select Operation

↓

Perform Arithmetic or Logic

↓

Output Result

↓

Set Flags (Zero, Carry, Overflow)

The ALU takes two inputs and control signals to select an operation, performs the operation, outputs the result, and sets status flags.

Execution Sample

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ALU is
  Port ( A, B : in STD_LOGIC_VECTOR(3 downto 0);
         Op : in STD_LOGIC_VECTOR(2 downto 0);
         Result : out STD_LOGIC_VECTOR(3 downto 0);
         Zero : out STD_LOGIC);
end ALU;

This VHDL code defines an ALU entity with 4-bit inputs A and B, a 3-bit operation code, a 4-bit result output, and a zero flag output.

Execution Table

Step	Inputs (A, B, Op)	Operation Selected	Computation	Result	Zero Flag
1	A=0011, B=0001, Op=000	Addition	3 + 1	0100	0
2	A=0101, B=0011, Op=001	Subtraction	5 - 3	0010	0
3	A=1111, B=0000, Op=010	AND	1111 AND 0000	0000	1
4	A=1010, B=0101, Op=011	OR	1010 OR 0101	1111	0
5	A=1001, B=0110, Op=100	XOR	1001 XOR 0110	1111	0
6	A=0000, B=0000, Op=000	Addition	0 + 0	0000	1
Exit	-	-	-	-	Execution ends after all test cases

💡 All test cases executed, ALU operations demonstrated.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5	After 6	Final
A	----	0011	0101	1111	1010	1001	0000	0000
B	----	0001	0011	0000	0101	0110	0000	0000
Op	----	000	001	010	011	100	000	000
Result	----	0100	0010	0000	1111	1111	0000	0000
Zero	----	0	0	1	0	0	1	1

Key Moments - 3 Insights

Why does the Zero flag become '1' when the result is 0000?

The Zero flag is set to '1' when the ALU output is all zeros, indicating the result is zero, as shown in execution_table rows 3 and 6.

How does the ALU know which operation to perform?

The ALU uses the Op input as a control signal to select the operation, demonstrated in the 'Operation Selected' column of the execution_table.

Why is the result different for the same inputs with different Op codes?

Because the Op code changes the operation (add, subtract, AND, OR, XOR), the same inputs produce different results, as seen in rows 1 to 5.

Visual Quiz - 3 Questions

Look at the execution_table, what is the Result when A=1010, B=0101, and Op=011?

A 1010

B 0101

C 1111

D 0000

💡 Hint

Check row 4 in the execution_table under Result.

At which step does the Zero flag first become '1'?

A Step 1

B Step 3

C Step 5

D Step 2

💡 Hint

Look at the Zero Flag column in execution_table rows.

If Op=000 always means addition, what would be the Result for A=0100 and B=0011?

A 0111

B 0011

C 0100

D 0000

💡 Hint

Addition sums the two inputs; see how addition works in execution_table row 1.

Concept Snapshot

ALU Design in VHDL:
- Inputs: A, B (4-bit), Op (3-bit control)
- Output: Result (4-bit), Zero flag
- Op selects operation: 000=Add, 001=Sub, 010=AND, 011=OR, 100=XOR
- Result computed based on Op
- Zero flag set if Result is zero
- Simple, modular, and extensible design

Full Transcript

This visual execution traces a simple 4-bit ALU design in VHDL. The ALU takes two 4-bit inputs A and B, and a 3-bit operation code Op. Depending on Op, it performs addition, subtraction, AND, OR, or XOR. The result is output as a 4-bit vector, and a Zero flag is set if the result is zero. The execution table shows step-by-step inputs, selected operation, computation, result, and zero flag status for six test cases. Variable tracking shows how inputs and outputs change each step. Key moments clarify why the Zero flag is set and how Op controls the operation. The quiz tests understanding of results and flags from the table. The snapshot summarizes the ALU design essentials in VHDL.

Practice

1. What is the main purpose of an ALU (Arithmetic Logic Unit) in a VHDL design?

easy

A. To perform arithmetic and logic operations on input data

B. To store data permanently

C. To control the flow of data between memory and CPU

D. To generate clock signals for synchronization

Solution

1. Step 1: Understand ALU function

   An ALU is designed to perform arithmetic (like addition) and logic (like AND, OR) operations on data inputs.

2. Step 2: Compare options with ALU role

   Only To perform arithmetic and logic operations on input data describes performing arithmetic and logic operations, which matches the ALU's purpose.

3. Final Answer:

   To perform arithmetic and logic operations on input data -> Option A

4. Quick Check:

   ALU = Arithmetic and Logic operations [OK]

Hint: ALU = math + logic on numbers inside chip [OK]

Common Mistakes:

• Confusing ALU with memory or control units
• Thinking ALU stores data permanently
• Assuming ALU generates clock signals

2. Which VHDL statement correctly selects an ALU operation based on a 2-bit control signal ALU_Sel?

easy

A. if ALU_Sel = 0 then result <= A + B; else result <= A - B; end if;

B. case ALU_Sel is when "00" => result <= A + B; when "01" => result <= A - B; end case;

C. switch(ALU_Sel) { case 0: result = A + B; break; case 1: result = A - B; }

D. select ALU_Sel when 0 => result <= A + B; when 1 => result <= A - B;

Solution

1. Step 1: Identify correct VHDL syntax for selection

   VHDL uses case ... is ... when ... => ... end case; for multi-way selection.

2. Step 2: Check options for correct syntax

   case ALU_Sel is when "00" => result <= A + B; when "01" => result <= A - B; end case; uses correct VHDL case syntax with bit string conditions. if ALU_Sel = 0 then result <= A + B; else result <= A - B; end if; uses if but compares to integer 0, which is invalid for std_logic_vector. switch(ALU_Sel) { case 0: result = A + B; break; case 1: result = A - B; } is not VHDL syntax (looks like C). select ALU_Sel when 0 => result <= A + B; when 1 => result <= A - B; uses invalid select syntax.

3. Final Answer:

   case ALU_Sel is when "00" => result <= A + B; when "01" => result <= A - B; end case; -> Option B

4. Quick Check:

   VHDL case syntax = case ALU_Sel is when "00" => result <= A + B; when "01" => result <= A - B; end case; [OK]

Hint: Use 'case ... is' for multi-bit control signals in VHDL [OK]

Common Mistakes:

• Using if with vector compared to integer
• Writing C-style switch in VHDL
• Incorrect select statement syntax

3. Given this VHDL snippet inside an ALU process:

case ALU_Sel is
  when "00" => result <= A + B;
  when "01" => result <= A and B;
  when others => result <= (others => '0');
end case;

If A = "1010", B = "1100", and ALU_Sel = "01", what is the value of result?

medium

A. "1000"

B. "1010"

C. "1110"

D. "0000"

Solution

1. Step 1: Identify operation for ALU_Sel = "01"

   The code says when ALU_Sel is "01", result <= A and B (bitwise AND).

2. Step 2: Calculate bitwise AND of A and B

   A = 1010, B = 1100
   Bitwise AND: 1&1=1, 0&1=0, 1&0=0, 0&0=0
   Result = 1000

3. Final Answer:

   "1000" -> Option A

4. Quick Check:

   Bitwise AND of 1010 & 1100 = 1000 [OK]

Hint: AND bits: 1&1=1 else 0 [OK]

Common Mistakes:

• Confusing AND with OR operation
• Mixing bit order in result
• Using decimal instead of binary

4. Identify the error in this VHDL ALU code snippet:

process(A, B, ALU_Sel)
begin
  case ALU_Sel is
    when "00" => result <= A + B;
    when "01" => result <= A - B;
    when others => result <= '0';
  end case;
end process;

medium

A. The case statement must use integers, not strings

B. The process sensitivity list is missing 'result'

C. The subtraction operator '-' is not allowed in VHDL

D. The 'when others' assignment uses a single bit '0' instead of a vector

Solution

1. Step 1: Check 'when others' assignment type

   The signal result is likely a vector (like std_logic_vector). Assigning a single bit '0' is a type mismatch.

2. Step 2: Confirm correct vector assignment

   To assign all bits zero, use (others => '0') instead of single '0'.

3. Final Answer:

   The 'when others' assignment uses a single bit '0' instead of a vector -> Option D

4. Quick Check:

   Vector needs (others => '0'), not '0' [OK]

Hint: Assign vectors with (others => '0'), not single quotes [OK]

Common Mistakes:

• Assigning single bit to vector signal
• Ignoring sensitivity list correctness
• Thinking '-' operator is invalid in VHDL

5. You want to extend an ALU to support a new operation: bitwise XOR when ALU_Sel = "10". Which VHDL code snippet correctly adds this operation inside the existing case statement?

case ALU_Sel is
  when "00" => result <= A + B;
  when "01" => result <= A - B;
  when others => result <= (others => '0');
end case;

hard

A. Add when "10" => result <= A or B; before when others

B. Replace when others with when "10" => result <= A xor B;

C. Add when "10" => result <= A xor B; before when others

D. Add when "10" => result <= A and B; after when others

Solution

1. Step 1: Understand case statement order

   Specific cases must be before when others because when others catches all unmatched cases.

2. Step 2: Add correct XOR operation for ALU_Sel = "10"

   Use when "10" => result <= A xor B; before when others to add XOR operation.

3. Final Answer:

   Add when "10" => result <= A xor B; before when others -> Option C

4. Quick Check:

   New case before others = Add when "10" => result <= A xor B; before when others [OK]

Hint: Put new cases before 'when others' in case statements [OK]

Common Mistakes:

• Replacing 'when others' instead of adding case
• Adding cases after 'when others' (ignored)
• Using wrong operation (OR or AND instead of XOR)