ALU design in VHDL - Step-by-Step Execution

Concept Flow - ALU design

Input A, Input B, Control Signals

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Select Operation

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Perform Arithmetic or Logic

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Output Result

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Set Flags (Zero, Carry, Overflow)

The ALU takes two inputs and control signals to select an operation, performs the operation, outputs the result, and sets status flags.

Execution Sample

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ALU is
  Port ( A, B : in STD_LOGIC_VECTOR(3 downto 0);
         Op : in STD_LOGIC_VECTOR(2 downto 0);
         Result : out STD_LOGIC_VECTOR(3 downto 0);
         Zero : out STD_LOGIC);
end ALU;

This VHDL code defines an ALU entity with 4-bit inputs A and B, a 3-bit operation code, a 4-bit result output, and a zero flag output.

Execution Table

Step	Inputs (A, B, Op)	Operation Selected	Computation	Result	Zero Flag
1	A=0011, B=0001, Op=000	Addition	3 + 1	0100	0
2	A=0101, B=0011, Op=001	Subtraction	5 - 3	0010	0
3	A=1111, B=0000, Op=010	AND	1111 AND 0000	0000	1
4	A=1010, B=0101, Op=011	OR	1010 OR 0101	1111	0
5	A=1001, B=0110, Op=100	XOR	1001 XOR 0110	1111	0
6	A=0000, B=0000, Op=000	Addition	0 + 0	0000	1
Exit	-	-	-	-	Execution ends after all test cases

💡 All test cases executed, ALU operations demonstrated.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5	After 6	Final
A	----	0011	0101	1111	1010	1001	0000	0000
B	----	0001	0011	0000	0101	0110	0000	0000
Op	----	000	001	010	011	100	000	000
Result	----	0100	0010	0000	1111	1111	0000	0000
Zero	----	0	0	1	0	0	1	1

Key Moments - 3 Insights

Why does the Zero flag become '1' when the result is 0000?

The Zero flag is set to '1' when the ALU output is all zeros, indicating the result is zero, as shown in execution_table rows 3 and 6.

How does the ALU know which operation to perform?

The ALU uses the Op input as a control signal to select the operation, demonstrated in the 'Operation Selected' column of the execution_table.

Why is the result different for the same inputs with different Op codes?

Because the Op code changes the operation (add, subtract, AND, OR, XOR), the same inputs produce different results, as seen in rows 1 to 5.

Visual Quiz - 3 Questions

Look at the execution_table, what is the Result when A=1010, B=0101, and Op=011?

A 1010

B 0101

C 1111

D 0000

💡 Hint

Check row 4 in the execution_table under Result.

At which step does the Zero flag first become '1'?

A Step 1

B Step 3

C Step 5

D Step 2

💡 Hint

Look at the Zero Flag column in execution_table rows.

If Op=000 always means addition, what would be the Result for A=0100 and B=0011?

A 0111

B 0011

C 0100

D 0000

💡 Hint

Addition sums the two inputs; see how addition works in execution_table row 1.

Concept Snapshot

ALU Design in VHDL:
- Inputs: A, B (4-bit), Op (3-bit control)
- Output: Result (4-bit), Zero flag
- Op selects operation: 000=Add, 001=Sub, 010=AND, 011=OR, 100=XOR
- Result computed based on Op
- Zero flag set if Result is zero
- Simple, modular, and extensible design

Full Transcript

This visual execution traces a simple 4-bit ALU design in VHDL. The ALU takes two 4-bit inputs A and B, and a 3-bit operation code Op. Depending on Op, it performs addition, subtraction, AND, OR, or XOR. The result is output as a 4-bit vector, and a Zero flag is set if the result is zero. The execution table shows step-by-step inputs, selected operation, computation, result, and zero flag status for six test cases. Variable tracking shows how inputs and outputs change each step. Key moments clarify why the Zero flag is set and how Op controls the operation. The quiz tests understanding of results and flags from the table. The snapshot summarizes the ALU design essentials in VHDL.