ALU design in VHDL - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a 4-bit input signal named 'A'.

VHDL

signal A : std_logic_vector([1] downto 0);

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A7

B4

C3

D1

Attempts:

3 left

💡 Hint

Common Mistakes

Using 4 downto 0 which creates 5 bits instead of 4.

Using 7 downto 0 which is 8 bits.

The signal 'A' is declared as a 4-bit vector, so the highest index is 3 (0 to 3).

2fill in blank

medium

Complete the code to perform bitwise AND on inputs A and B and assign to output Result.

VHDL

Result <= A [1] B;

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Aand

Bor

Cxor

Dnand

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'or' instead of 'and'.

Using 'xor' which is exclusive or.

The bitwise AND operation in VHDL is done using the keyword 'and'.

3fill in blank

hard

Fix the error in the process sensitivity list to include all inputs A, B, and Op.

VHDL

process([1])
begin
  -- ALU operation code
end process;

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AA, B

BA

COp

DA, B, Op

Attempts:

3 left

💡 Hint

Common Mistakes

Leaving out 'Op' from the sensitivity list.

Including only one or two inputs.

The process must be sensitive to all inputs that affect the output: A, B, and Op.

4fill in blank

hard

Fill both blanks to complete the case statement for ALU operations.

VHDL

case Op is
  when "00" => Result <= A [1] B;
  when "01" => Result <= A [2] B;
  when others => Result <= (others => '0');
end case;

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Aand

Bor

Cxor

Dnand

Attempts:

3 left

💡 Hint

Common Mistakes

Swapping AND and OR operations.

Using XOR or NAND incorrectly.

The ALU performs AND when Op is "00" and OR when Op is "01".

5fill in blank

hard

Fill all three blanks to complete the ALU output assignment with addition and subtraction.

VHDL

case Op is
  when "10" => Result <= std_logic_vector(unsigned(A) [1] unsigned(B));
  when "11" => Result <= std_logic_vector(unsigned(A) [2] unsigned(B));
  when others => Result <= (others => '0');
end case;
-- Note: [3] is used for type conversion.

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A+

B-

Cunsigned

Dstd_logic_vector

Attempts:

3 left

💡 Hint

Common Mistakes

Using std_logic_vector instead of unsigned for arithmetic.

Mixing up addition and subtraction operators.

Use '+' for addition and '-' for subtraction on unsigned types. The 'unsigned' function converts std_logic_vector to unsigned for arithmetic.