ALU design in VHDL - Mini Project: Build & Apply

ALU Design in VHDL

📖 Scenario: You are designing a simple Arithmetic Logic Unit (ALU) for a small digital system. The ALU will perform basic operations like addition, subtraction, AND, and OR on two 4-bit inputs.

🎯 Goal: Build a VHDL module for an ALU that takes two 4-bit inputs and a 2-bit operation selector, then outputs the 4-bit result of the selected operation.

📋 What You'll Learn

Create two 4-bit input signals named A and B.

Create a 2-bit input signal named Op to select the operation.

Implement the ALU logic to perform addition, subtraction, AND, and OR based on Op.

Output the 4-bit result on a signal named Result.

💡 Why This Matters

🌍 Real World

ALUs are the core of all processors and digital systems, performing arithmetic and logic operations on data.

💼 Career

Understanding ALU design is essential for hardware engineers and FPGA developers working on digital circuit design.

1

DATA SETUP: Define inputs and output signals

Write the VHDL code to declare a 4-bit input signal A, a 4-bit input signal B, a 2-bit input signal Op, and a 4-bit output signal Result inside an entity named SimpleALU.

VHDL

entity SimpleALU is
    Port (
        -- Declare inputs and output here
    );
end SimpleALU;

Need a hint?

Use std_logic_vector(3 downto 0) for 4-bit signals and std_logic_vector(1 downto 0) for 2-bit signals.

2

CONFIGURATION: Create architecture and signal for internal calculation

Write the VHDL code to start the architecture named Behavioral for SimpleALU and declare an internal 5-bit signal named temp_result to hold intermediate results.

VHDL

entity SimpleALU is
    Port (
        A : in std_logic_vector(3 downto 0);
        B : in std_logic_vector(3 downto 0);
        Op : in std_logic_vector(1 downto 0);
        Result : out std_logic_vector(3 downto 0)
    );
end SimpleALU;

architecture Behavioral of SimpleALU is
    -- Declare internal signal here
begin

end Behavioral;

Need a hint?

Use a 5-bit vector for temp_result to hold carry or borrow bits during addition or subtraction.

3

CORE LOGIC: Implement ALU operations using a process and case statement

Inside the architecture Behavioral, write a process that triggers on changes to A, B, or Op. Use a case statement on Op to assign temp_result as follows: "00" for addition (A + B), "01" for subtraction (A - B), "10" for bitwise AND (A and B), and "11" for bitwise OR (A or B). Then assign the lower 4 bits of temp_result to Result.

VHDL

entity SimpleALU is
    Port (
        A : in std_logic_vector(3 downto 0);
        B : in std_logic_vector(3 downto 0);
        Op : in std_logic_vector(1 downto 0);
        Result : out std_logic_vector(3 downto 0)
    );
end SimpleALU;

architecture Behavioral of SimpleALU is
    signal temp_result : std_logic_vector(4 downto 0);
begin
    -- Write process and case statement here
end Behavioral;

Need a hint?

Use unsigned() conversion for arithmetic operations and assign the 4-bit result to Result.

4

OUTPUT: Test the ALU by printing the result for a sample input

Write a simple testbench process inside the architecture Behavioral that assigns A = "0011", B = "0001", and Op = "00" (addition). Then output the value of Result using report statement to display the result as a string.

VHDL

entity SimpleALU is
    Port (
        A : in std_logic_vector(3 downto 0);
        B : in std_logic_vector(3 downto 0);
        Op : in std_logic_vector(1 downto 0);
        Result : out std_logic_vector(3 downto 0)
    );
end SimpleALU;

architecture Behavioral of SimpleALU is
    signal temp_result : std_logic_vector(4 downto 0);
    signal A : std_logic_vector(3 downto 0);
    signal B : std_logic_vector(3 downto 0);
    signal Op : std_logic_vector(1 downto 0);
    signal Result : std_logic_vector(3 downto 0);
begin
    process(A, B, Op)
    begin
        case Op is
            when "00" =>  -- Addition
                temp_result   -- Subtraction
                temp_result   -- AND
                temp_result(3 downto 0)   -- OR
                temp_result(3 downto 0) <= A or B;
                temp_result(4) <= '0';
        end case;
        Result <= temp_result(3 downto 0);
    end process;

    -- Your code here
end Behavioral;

Need a hint?

Use a test process to assign values and a report statement to print the result as an integer.