ALU design in VHDL - Mini Project: Build & Apply

ALU Design in VHDL

📖 Scenario: You are designing a simple Arithmetic Logic Unit (ALU) for a small digital system. The ALU will perform basic operations like addition, subtraction, AND, and OR on two 4-bit inputs.

🎯 Goal: Build a VHDL module for an ALU that takes two 4-bit inputs and a 2-bit operation selector, then outputs the 4-bit result of the selected operation.

📋 What You'll Learn

Create two 4-bit input signals named A and B.

Create a 2-bit input signal named Op to select the operation.

Implement the ALU logic to perform addition, subtraction, AND, and OR based on Op.

Output the 4-bit result on a signal named Result.

💡 Why This Matters

🌍 Real World

ALUs are the core of all processors and digital systems, performing arithmetic and logic operations on data.

💼 Career

Understanding ALU design is essential for hardware engineers and FPGA developers working on digital circuit design.

1

DATA SETUP: Define inputs and output signals

Write the VHDL code to declare a 4-bit input signal A, a 4-bit input signal B, a 2-bit input signal Op, and a 4-bit output signal Result inside an entity named SimpleALU.

VHDL

entity SimpleALU is
    Port (
        -- Declare inputs and output here
    );
end SimpleALU;

Hint

Use std_logic_vector(3 downto 0) for 4-bit signals and std_logic_vector(1 downto 0) for 2-bit signals.

2

CONFIGURATION: Create architecture and signal for internal calculation

Write the VHDL code to start the architecture named Behavioral for SimpleALU and declare an internal 5-bit signal named temp_result to hold intermediate results.

VHDL

entity SimpleALU is
    Port (
        A : in std_logic_vector(3 downto 0);
        B : in std_logic_vector(3 downto 0);
        Op : in std_logic_vector(1 downto 0);
        Result : out std_logic_vector(3 downto 0)
    );
end SimpleALU;

architecture Behavioral of SimpleALU is
    -- Declare internal signal here
begin

end Behavioral;

Hint

Use a 5-bit vector for temp_result to hold carry or borrow bits during addition or subtraction.

3

CORE LOGIC: Implement ALU operations using a process and case statement

Inside the architecture Behavioral, write a process that triggers on changes to A, B, or Op. Use a case statement on Op to assign temp_result as follows: "00" for addition (A + B), "01" for subtraction (A - B), "10" for bitwise AND (A and B), and "11" for bitwise OR (A or B). Then assign the lower 4 bits of temp_result to Result.

VHDL

entity SimpleALU is
    Port (
        A : in std_logic_vector(3 downto 0);
        B : in std_logic_vector(3 downto 0);
        Op : in std_logic_vector(1 downto 0);
        Result : out std_logic_vector(3 downto 0)
    );
end SimpleALU;

architecture Behavioral of SimpleALU is
    signal temp_result : std_logic_vector(4 downto 0);
begin
    -- Write process and case statement here
end Behavioral;

Hint

Use unsigned() conversion for arithmetic operations and assign the 4-bit result to Result.

4

OUTPUT: Test the ALU by printing the result for a sample input

Write a simple testbench process inside the architecture Behavioral that assigns A = "0011", B = "0001", and Op = "00" (addition). Then output the value of Result using report statement to display the result as a string.

VHDL

entity SimpleALU is
    Port (
        A : in std_logic_vector(3 downto 0);
        B : in std_logic_vector(3 downto 0);
        Op : in std_logic_vector(1 downto 0);
        Result : out std_logic_vector(3 downto 0)
    );
end SimpleALU;

architecture Behavioral of SimpleALU is
    signal temp_result : std_logic_vector(4 downto 0);
    signal A : std_logic_vector(3 downto 0);
    signal B : std_logic_vector(3 downto 0);
    signal Op : std_logic_vector(1 downto 0);
    signal Result : std_logic_vector(3 downto 0);
begin
    process(A, B, Op)
    begin
        case Op is
            when "00" =>  -- Addition
                temp_result   -- Subtraction
                temp_result   -- AND
                temp_result(3 downto 0)   -- OR
                temp_result(3 downto 0) <= A or B;
                temp_result(4) <= '0';
        end case;
        Result <= temp_result(3 downto 0);
    end process;

    -- Your code here
end Behavioral;

Hint

Use a test process to assign values and a report statement to print the result as an integer.

Practice

1. What is the main purpose of an ALU (Arithmetic Logic Unit) in a VHDL design?

easy

A. To perform arithmetic and logic operations on input data

B. To store data permanently

C. To control the flow of data between memory and CPU

D. To generate clock signals for synchronization

Solution

1. Step 1: Understand ALU function

   An ALU is designed to perform arithmetic (like addition) and logic (like AND, OR) operations on data inputs.

2. Step 2: Compare options with ALU role

   Only To perform arithmetic and logic operations on input data describes performing arithmetic and logic operations, which matches the ALU's purpose.

3. Final Answer:

   To perform arithmetic and logic operations on input data -> Option A

4. Quick Check:

   ALU = Arithmetic and Logic operations [OK]

Hint: ALU = math + logic on numbers inside chip [OK]

Common Mistakes:

• Confusing ALU with memory or control units
• Thinking ALU stores data permanently
• Assuming ALU generates clock signals

2. Which VHDL statement correctly selects an ALU operation based on a 2-bit control signal ALU_Sel?

easy

A. if ALU_Sel = 0 then result <= A + B; else result <= A - B; end if;

B. case ALU_Sel is when "00" => result <= A + B; when "01" => result <= A - B; end case;

C. switch(ALU_Sel) { case 0: result = A + B; break; case 1: result = A - B; }

D. select ALU_Sel when 0 => result <= A + B; when 1 => result <= A - B;

Solution

1. Step 1: Identify correct VHDL syntax for selection

   VHDL uses case ... is ... when ... => ... end case; for multi-way selection.

2. Step 2: Check options for correct syntax

   case ALU_Sel is when "00" => result <= A + B; when "01" => result <= A - B; end case; uses correct VHDL case syntax with bit string conditions. if ALU_Sel = 0 then result <= A + B; else result <= A - B; end if; uses if but compares to integer 0, which is invalid for std_logic_vector. switch(ALU_Sel) { case 0: result = A + B; break; case 1: result = A - B; } is not VHDL syntax (looks like C). select ALU_Sel when 0 => result <= A + B; when 1 => result <= A - B; uses invalid select syntax.

3. Final Answer:

   case ALU_Sel is when "00" => result <= A + B; when "01" => result <= A - B; end case; -> Option B

4. Quick Check:

   VHDL case syntax = case ALU_Sel is when "00" => result <= A + B; when "01" => result <= A - B; end case; [OK]

Hint: Use 'case ... is' for multi-bit control signals in VHDL [OK]

Common Mistakes:

• Using if with vector compared to integer
• Writing C-style switch in VHDL
• Incorrect select statement syntax

3. Given this VHDL snippet inside an ALU process:

case ALU_Sel is
  when "00" => result <= A + B;
  when "01" => result <= A and B;
  when others => result <= (others => '0');
end case;

If A = "1010", B = "1100", and ALU_Sel = "01", what is the value of result?

medium

A. "1000"

B. "1010"

C. "1110"

D. "0000"

Solution

1. Step 1: Identify operation for ALU_Sel = "01"

   The code says when ALU_Sel is "01", result <= A and B (bitwise AND).

2. Step 2: Calculate bitwise AND of A and B

   A = 1010, B = 1100
   Bitwise AND: 1&1=1, 0&1=0, 1&0=0, 0&0=0
   Result = 1000

3. Final Answer:

   "1000" -> Option A

4. Quick Check:

   Bitwise AND of 1010 & 1100 = 1000 [OK]

Hint: AND bits: 1&1=1 else 0 [OK]

Common Mistakes:

• Confusing AND with OR operation
• Mixing bit order in result
• Using decimal instead of binary

4. Identify the error in this VHDL ALU code snippet:

process(A, B, ALU_Sel)
begin
  case ALU_Sel is
    when "00" => result <= A + B;
    when "01" => result <= A - B;
    when others => result <= '0';
  end case;
end process;

medium

A. The case statement must use integers, not strings

B. The process sensitivity list is missing 'result'

C. The subtraction operator '-' is not allowed in VHDL

D. The 'when others' assignment uses a single bit '0' instead of a vector

Solution

1. Step 1: Check 'when others' assignment type

   The signal result is likely a vector (like std_logic_vector). Assigning a single bit '0' is a type mismatch.

2. Step 2: Confirm correct vector assignment

   To assign all bits zero, use (others => '0') instead of single '0'.

3. Final Answer:

   The 'when others' assignment uses a single bit '0' instead of a vector -> Option D

4. Quick Check:

   Vector needs (others => '0'), not '0' [OK]

Hint: Assign vectors with (others => '0'), not single quotes [OK]

Common Mistakes:

• Assigning single bit to vector signal
• Ignoring sensitivity list correctness
• Thinking '-' operator is invalid in VHDL

5. You want to extend an ALU to support a new operation: bitwise XOR when ALU_Sel = "10". Which VHDL code snippet correctly adds this operation inside the existing case statement?

case ALU_Sel is
  when "00" => result <= A + B;
  when "01" => result <= A - B;
  when others => result <= (others => '0');
end case;

hard

A. Add when "10" => result <= A or B; before when others

B. Replace when others with when "10" => result <= A xor B;

C. Add when "10" => result <= A xor B; before when others

D. Add when "10" => result <= A and B; after when others

Solution

1. Step 1: Understand case statement order

   Specific cases must be before when others because when others catches all unmatched cases.

2. Step 2: Add correct XOR operation for ALU_Sel = "10"

   Use when "10" => result <= A xor B; before when others to add XOR operation.

3. Final Answer:

   Add when "10" => result <= A xor B; before when others -> Option C

4. Quick Check:

   New case before others = Add when "10" => result <= A xor B; before when others [OK]

Hint: Put new cases before 'when others' in case statements [OK]

Common Mistakes:

• Replacing 'when others' instead of adding case
• Adding cases after 'when others' (ignored)
• Using wrong operation (OR or AND instead of XOR)