ALU design in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of a 4-bit ALU performing addition

Given the following VHDL snippet for a 4-bit ALU performing addition, what is the output when A = "0101" and B = "0011"?

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity ALU is
    Port ( A : in STD_LOGIC_VECTOR(3 downto 0);
           B : in STD_LOGIC_VECTOR(3 downto 0);
           Result : out STD_LOGIC_VECTOR(3 downto 0);
           CarryOut : out STD_LOGIC);
end ALU;

architecture Behavioral of ALU is
begin
    process(A, B)
        variable sum : UNSIGNED(4 downto 0);
    begin
        sum := ('0' & unsigned(A)) + ('0' & unsigned(B));
        Result <= std_logic_vector(sum(3 downto 0));
        CarryOut <= sum(4);
    end process;
end Behavioral;

A Result = "1000", CarryOut = '0'

B Result = "1111", CarryOut = '0'

C Result = "1000", CarryOut = '1'

D Result = "0110", CarryOut = '0'

💡 Hint

Remember to consider the carry out bit when adding two 4-bit numbers.

Adding 0101 (5) and 0011 (3) gives 8 (1000 in binary). Since 5 + 3 = 8 fits in 4 bits without overflow, CarryOut is '0'. The sum variable is 5 bits wide, so the carry bit is 0. The correct answer is Result = "1000", CarryOut = '0'.

❓ Predict Output

intermediate

Output of ALU performing bitwise AND

What is the output Result of the ALU performing bitwise AND on inputs A = "1100" and B = "1010"?

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity ALU_AND is
    Port ( A : in STD_LOGIC_VECTOR(3 downto 0);
           B : in STD_LOGIC_VECTOR(3 downto 0);
           Result : out STD_LOGIC_VECTOR(3 downto 0));
end ALU_AND;

architecture Behavioral of ALU_AND is
begin
    Result <= A and B;
end Behavioral;

A Result = "1000"

B Result = "1110"

C Result = "0100"

D Result = "1010"

💡 Hint

Bitwise AND outputs 1 only if both bits are 1.

Performing bitwise AND on 1100 and 1010 results in 1000 because only the first bit is 1 in both inputs.

🔧 Debug

advanced

Identify the error in ALU subtraction process

The following VHDL code is intended to perform subtraction (A - B) in a 4-bit ALU. What error will occur when compiling or running this code?

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity ALU_Sub is
    Port ( A : in STD_LOGIC_VECTOR(3 downto 0);
           B : in STD_LOGIC_VECTOR(3 downto 0);
           Result : out STD_LOGIC_VECTOR(3 downto 0);
           BorrowOut : out STD_LOGIC);
end ALU_Sub;

architecture Behavioral of ALU_Sub is
begin
    process(A, B)
        variable diff : UNSIGNED(3 downto 0);
    begin
        diff := unsigned(A) - unsigned(B);
        Result <= std_logic_vector(diff);
        BorrowOut <= '0';
    end process;
end Behavioral;

A Compilation error due to unsigned subtraction possibly resulting in negative value

B Runtime error due to overflow in subtraction

C No error, code runs correctly

D BorrowOut is always zero, so incorrect borrow detection

💡 Hint

Check how borrow is detected and reported in subtraction.

The code does not compute or assign the BorrowOut signal properly. It is always set to '0', so borrow detection is missing.

📝 Syntax

advanced

Identify the syntax error in ALU operation selection

Which option contains the correct syntax for a VHDL case statement selecting ALU operations based on a 2-bit control signal ALU_Sel?

VHDL

process(ALU_Sel, A, B)
begin
    case ALU_Sel is
        when "00" => Result <= A + B;
        when "01" => Result <= A - B;
        when "10" => Result <= A and B;
        when "11" => Result <= A or B;
        when others => Result <= (others => '0');
    end case;
end process;

A

case ALU_Sel is
  when "00" => Result <= A + B;
  when "01" => Result <= A - B;
  when "10" => Result <= A and B;
  when "11" => Result <= A or B;
end case;

B

case ALU_Sel is
  when "00" => Result <= A + B;
  when "01" => Result <= A - B;
  when "10" => Result <= A and B;
  when "11" => Result <= A or B;
  when others => Result <= (others => '0');
end case;

C

case ALU_Sel is
  when "00" => Result <= A + B
  when "01" => Result <= A - B;
  when "10" => Result <= A and B;
  when "11" => Result <= A or B;
  when others => Result <= (others => '0');
end case;

D

case ALU_Sel is
  when 0 => Result <= A + B;
  when 1 => Result <= A - B;
  when 2 => Result <= A and B;
  when 3 => Result <= A or B;
  when others => Result <= (others => '0');
end case;

💡 Hint

Check for missing semicolons and correct use of when others.

Option B is correct syntax: all when statements end with semicolons and when others is included. Option B uses integers instead of bit strings, which is invalid. Option B misses when others clause. Option B misses semicolon after first when statement.

🚀 Application

expert

Determine the output of a combined ALU operation with overflow detection

Consider a 4-bit ALU that performs addition or subtraction based on a control signal Op (0 for addition, 1 for subtraction). The ALU outputs Result (4 bits), CarryOut, and Overflow signals. Given inputs A = "0111" (7), B = "1001" (9), and Op = 1 (subtraction), what are the values of Result, CarryOut, and Overflow?

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity ALU_Adv is
    Port ( A : in STD_LOGIC_VECTOR(3 downto 0);
           B : in STD_LOGIC_VECTOR(3 downto 0);
           Op : in STD_LOGIC; -- 0: add, 1: subtract
           Result : out STD_LOGIC_VECTOR(3 downto 0);
           CarryOut : out STD_LOGIC;
           Overflow : out STD_LOGIC);
end ALU_Adv;

architecture Behavioral of ALU_Adv is
    signal A_unsigned, B_unsigned, B_inverted : UNSIGNED(3 downto 0);
    signal sum : UNSIGNED(4 downto 0);
begin
    A_unsigned <= unsigned(A);
    B_inverted <= (others => '0');
    process(A_unsigned, B_unsigned, Op)
    begin
        B_unsigned <= unsigned(B);
        if Op = '1' then
            B_inverted <= not B_unsigned;
            sum <= ('0' & A_unsigned) + ('0' & B_inverted) + 1;
        else
            sum <= ('0' & A_unsigned) + ('0' & B_unsigned);
        end if;
        Result <= std_logic_vector(sum(3 downto 0));
        CarryOut <= sum(4);
        Overflow <= (A_unsigned(3) xor B_inverted(3)) and (A_unsigned(3) xor sum(3));
    end process;
end Behavioral;

A Result = "1110", CarryOut = '1', Overflow = '0'

B Result = "1110", CarryOut = '0', Overflow = '0'

C Result = "1110", CarryOut = '0', Overflow = '1'

D Result = "1000", CarryOut = '1', Overflow = '1'

💡 Hint

Check two's complement subtraction and overflow conditions carefully.

Subtracting 9 from 7 in 4-bit two's complement results in -2 (1110). CarryOut is 0 because borrow occurred. Overflow occurs because signs of operands differ and result sign differs from A's sign.