ALU design in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of a 4-bit ALU performing addition

Given the following VHDL snippet for a 4-bit ALU performing addition, what is the output when A = "0101" and B = "0011"?

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity ALU is
    Port ( A : in STD_LOGIC_VECTOR(3 downto 0);
           B : in STD_LOGIC_VECTOR(3 downto 0);
           Result : out STD_LOGIC_VECTOR(3 downto 0);
           CarryOut : out STD_LOGIC);
end ALU;

architecture Behavioral of ALU is
begin
    process(A, B)
        variable sum : UNSIGNED(4 downto 0);
    begin
        sum := ('0' & unsigned(A)) + ('0' & unsigned(B));
        Result <= std_logic_vector(sum(3 downto 0));
        CarryOut <= sum(4);
    end process;
end Behavioral;

A Result = "1000", CarryOut = '0'

B Result = "1111", CarryOut = '0'

C Result = "1000", CarryOut = '1'

D Result = "0110", CarryOut = '0'

💡 Hint

Remember to consider the carry out bit when adding two 4-bit numbers.

Adding 0101 (5) and 0011 (3) gives 8 (1000 in binary). Since 5 + 3 = 8 fits in 4 bits without overflow, CarryOut is '0'. The sum variable is 5 bits wide, so the carry bit is 0. The correct answer is Result = "1000", CarryOut = '0'.

❓ Predict Output

intermediate

Output of ALU performing bitwise AND

What is the output Result of the ALU performing bitwise AND on inputs A = "1100" and B = "1010"?

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity ALU_AND is
    Port ( A : in STD_LOGIC_VECTOR(3 downto 0);
           B : in STD_LOGIC_VECTOR(3 downto 0);
           Result : out STD_LOGIC_VECTOR(3 downto 0));
end ALU_AND;

architecture Behavioral of ALU_AND is
begin
    Result <= A and B;
end Behavioral;

A Result = "1000"

B Result = "1110"

C Result = "0100"

D Result = "1010"

💡 Hint

Bitwise AND outputs 1 only if both bits are 1.

Performing bitwise AND on 1100 and 1010 results in 1000 because only the first bit is 1 in both inputs.

🔧 Debug

advanced

Identify the error in ALU subtraction process

The following VHDL code is intended to perform subtraction (A - B) in a 4-bit ALU. What error will occur when compiling or running this code?

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity ALU_Sub is
    Port ( A : in STD_LOGIC_VECTOR(3 downto 0);
           B : in STD_LOGIC_VECTOR(3 downto 0);
           Result : out STD_LOGIC_VECTOR(3 downto 0);
           BorrowOut : out STD_LOGIC);
end ALU_Sub;

architecture Behavioral of ALU_Sub is
begin
    process(A, B)
        variable diff : UNSIGNED(3 downto 0);
    begin
        diff := unsigned(A) - unsigned(B);
        Result <= std_logic_vector(diff);
        BorrowOut <= '0';
    end process;
end Behavioral;

A Compilation error due to unsigned subtraction possibly resulting in negative value

B Runtime error due to overflow in subtraction

C No error, code runs correctly

D BorrowOut is always zero, so incorrect borrow detection

💡 Hint

Check how borrow is detected and reported in subtraction.

The code does not compute or assign the BorrowOut signal properly. It is always set to '0', so borrow detection is missing.

📝 Syntax

advanced

Identify the syntax error in ALU operation selection

Which option contains the correct syntax for a VHDL case statement selecting ALU operations based on a 2-bit control signal ALU_Sel?

VHDL

process(ALU_Sel, A, B)
begin
    case ALU_Sel is
        when "00" => Result <= A + B;
        when "01" => Result <= A - B;
        when "10" => Result <= A and B;
        when "11" => Result <= A or B;
        when others => Result <= (others => '0');
    end case;
end process;

A

case ALU_Sel is
  when "00" => Result <= A + B;
  when "01" => Result <= A - B;
  when "10" => Result <= A and B;
  when "11" => Result <= A or B;
end case;

B

case ALU_Sel is
  when "00" => Result <= A + B;
  when "01" => Result <= A - B;
  when "10" => Result <= A and B;
  when "11" => Result <= A or B;
  when others => Result <= (others => '0');
end case;

C

case ALU_Sel is
  when "00" => Result <= A + B
  when "01" => Result <= A - B;
  when "10" => Result <= A and B;
  when "11" => Result <= A or B;
  when others => Result <= (others => '0');
end case;

D

case ALU_Sel is
  when 0 => Result <= A + B;
  when 1 => Result <= A - B;
  when 2 => Result <= A and B;
  when 3 => Result <= A or B;
  when others => Result <= (others => '0');
end case;

💡 Hint

Check for missing semicolons and correct use of when others.

Option B is correct syntax: all when statements end with semicolons and when others is included. Option B uses integers instead of bit strings, which is invalid. Option B misses when others clause. Option B misses semicolon after first when statement.

🚀 Application

expert

Determine the output of a combined ALU operation with overflow detection

Consider a 4-bit ALU that performs addition or subtraction based on a control signal Op (0 for addition, 1 for subtraction). The ALU outputs Result (4 bits), CarryOut, and Overflow signals. Given inputs A = "0111" (7), B = "1001" (9), and Op = 1 (subtraction), what are the values of Result, CarryOut, and Overflow?

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity ALU_Adv is
    Port ( A : in STD_LOGIC_VECTOR(3 downto 0);
           B : in STD_LOGIC_VECTOR(3 downto 0);
           Op : in STD_LOGIC; -- 0: add, 1: subtract
           Result : out STD_LOGIC_VECTOR(3 downto 0);
           CarryOut : out STD_LOGIC;
           Overflow : out STD_LOGIC);
end ALU_Adv;

architecture Behavioral of ALU_Adv is
    signal A_unsigned, B_unsigned, B_inverted : UNSIGNED(3 downto 0);
    signal sum : UNSIGNED(4 downto 0);
begin
    A_unsigned <= unsigned(A);
    B_inverted <= (others => '0');
    process(A_unsigned, B_unsigned, Op)
    begin
        B_unsigned <= unsigned(B);
        if Op = '1' then
            B_inverted <= not B_unsigned;
            sum <= ('0' & A_unsigned) + ('0' & B_inverted) + 1;
        else
            sum <= ('0' & A_unsigned) + ('0' & B_unsigned);
        end if;
        Result <= std_logic_vector(sum(3 downto 0));
        CarryOut <= sum(4);
        Overflow <= (A_unsigned(3) xor B_inverted(3)) and (A_unsigned(3) xor sum(3));
    end process;
end Behavioral;

A Result = "1110", CarryOut = '1', Overflow = '0'

B Result = "1110", CarryOut = '0', Overflow = '0'

C Result = "1110", CarryOut = '0', Overflow = '1'

D Result = "1000", CarryOut = '1', Overflow = '1'

💡 Hint

Check two's complement subtraction and overflow conditions carefully.

Subtracting 9 from 7 in 4-bit two's complement results in -2 (1110). CarryOut is 0 because borrow occurred. Overflow occurs because signs of operands differ and result sign differs from A's sign.

Practice

1. What is the main purpose of an ALU (Arithmetic Logic Unit) in a VHDL design?

easy

A. To perform arithmetic and logic operations on input data

B. To store data permanently

C. To control the flow of data between memory and CPU

D. To generate clock signals for synchronization

Solution

1. Step 1: Understand ALU function

   An ALU is designed to perform arithmetic (like addition) and logic (like AND, OR) operations on data inputs.

2. Step 2: Compare options with ALU role

   Only To perform arithmetic and logic operations on input data describes performing arithmetic and logic operations, which matches the ALU's purpose.

3. Final Answer:

   To perform arithmetic and logic operations on input data -> Option A

4. Quick Check:

   ALU = Arithmetic and Logic operations [OK]

Hint: ALU = math + logic on numbers inside chip [OK]

Common Mistakes:

• Confusing ALU with memory or control units
• Thinking ALU stores data permanently
• Assuming ALU generates clock signals

2. Which VHDL statement correctly selects an ALU operation based on a 2-bit control signal ALU_Sel?

easy

A. if ALU_Sel = 0 then result <= A + B; else result <= A - B; end if;

B. case ALU_Sel is when "00" => result <= A + B; when "01" => result <= A - B; end case;

C. switch(ALU_Sel) { case 0: result = A + B; break; case 1: result = A - B; }

D. select ALU_Sel when 0 => result <= A + B; when 1 => result <= A - B;

Solution

1. Step 1: Identify correct VHDL syntax for selection

   VHDL uses case ... is ... when ... => ... end case; for multi-way selection.

2. Step 2: Check options for correct syntax

   case ALU_Sel is when "00" => result <= A + B; when "01" => result <= A - B; end case; uses correct VHDL case syntax with bit string conditions. if ALU_Sel = 0 then result <= A + B; else result <= A - B; end if; uses if but compares to integer 0, which is invalid for std_logic_vector. switch(ALU_Sel) { case 0: result = A + B; break; case 1: result = A - B; } is not VHDL syntax (looks like C). select ALU_Sel when 0 => result <= A + B; when 1 => result <= A - B; uses invalid select syntax.

3. Final Answer:

   case ALU_Sel is when "00" => result <= A + B; when "01" => result <= A - B; end case; -> Option B

4. Quick Check:

   VHDL case syntax = case ALU_Sel is when "00" => result <= A + B; when "01" => result <= A - B; end case; [OK]

Hint: Use 'case ... is' for multi-bit control signals in VHDL [OK]

Common Mistakes:

• Using if with vector compared to integer
• Writing C-style switch in VHDL
• Incorrect select statement syntax

3. Given this VHDL snippet inside an ALU process:

case ALU_Sel is
  when "00" => result <= A + B;
  when "01" => result <= A and B;
  when others => result <= (others => '0');
end case;

If A = "1010", B = "1100", and ALU_Sel = "01", what is the value of result?

medium

A. "1000"

B. "1010"

C. "1110"

D. "0000"

Solution

1. Step 1: Identify operation for ALU_Sel = "01"

   The code says when ALU_Sel is "01", result <= A and B (bitwise AND).

2. Step 2: Calculate bitwise AND of A and B

   A = 1010, B = 1100
   Bitwise AND: 1&1=1, 0&1=0, 1&0=0, 0&0=0
   Result = 1000

3. Final Answer:

   "1000" -> Option A

4. Quick Check:

   Bitwise AND of 1010 & 1100 = 1000 [OK]

Hint: AND bits: 1&1=1 else 0 [OK]

Common Mistakes:

• Confusing AND with OR operation
• Mixing bit order in result
• Using decimal instead of binary

4. Identify the error in this VHDL ALU code snippet:

process(A, B, ALU_Sel)
begin
  case ALU_Sel is
    when "00" => result <= A + B;
    when "01" => result <= A - B;
    when others => result <= '0';
  end case;
end process;

medium

A. The case statement must use integers, not strings

B. The process sensitivity list is missing 'result'

C. The subtraction operator '-' is not allowed in VHDL

D. The 'when others' assignment uses a single bit '0' instead of a vector

Solution

1. Step 1: Check 'when others' assignment type

   The signal result is likely a vector (like std_logic_vector). Assigning a single bit '0' is a type mismatch.

2. Step 2: Confirm correct vector assignment

   To assign all bits zero, use (others => '0') instead of single '0'.

3. Final Answer:

   The 'when others' assignment uses a single bit '0' instead of a vector -> Option D

4. Quick Check:

   Vector needs (others => '0'), not '0' [OK]

Hint: Assign vectors with (others => '0'), not single quotes [OK]

Common Mistakes:

• Assigning single bit to vector signal
• Ignoring sensitivity list correctness
• Thinking '-' operator is invalid in VHDL

5. You want to extend an ALU to support a new operation: bitwise XOR when ALU_Sel = "10". Which VHDL code snippet correctly adds this operation inside the existing case statement?

case ALU_Sel is
  when "00" => result <= A + B;
  when "01" => result <= A - B;
  when others => result <= (others => '0');
end case;

hard

A. Add when "10" => result <= A or B; before when others

B. Replace when others with when "10" => result <= A xor B;

C. Add when "10" => result <= A xor B; before when others

D. Add when "10" => result <= A and B; after when others

Solution

1. Step 1: Understand case statement order

   Specific cases must be before when others because when others catches all unmatched cases.

2. Step 2: Add correct XOR operation for ALU_Sel = "10"

   Use when "10" => result <= A xor B; before when others to add XOR operation.

3. Final Answer:

   Add when "10" => result <= A xor B; before when others -> Option C

4. Quick Check:

   New case before others = Add when "10" => result <= A xor B; before when others [OK]

Hint: Put new cases before 'when others' in case statements [OK]

Common Mistakes:

• Replacing 'when others' instead of adding case
• Adding cases after 'when others' (ignored)
• Using wrong operation (OR or AND instead of XOR)