Adder and subtractor design in VHDL - Step-by-Step Execution

Concept Flow - Adder and subtractor design

Input A, Input B, Control

↓

Check Control

↓

Perform A+B

↓

Output Result

The design checks a control signal to decide whether to add or subtract two inputs, then outputs the result.

Execution Sample

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity AdderSubtractor is
  port(
    A, B : in unsigned(3 downto 0);
    Control : in std_logic; -- 0 for add, 1 for subtract
    Result : out unsigned(3 downto 0)
  );
end entity;

architecture Behavioral of AdderSubtractor is
begin
  process(A, B, Control) is
  begin
    if Control = '0' then
      Result <= A + B;
    else
      Result <= A - B;
    end if;
  end process;
end Behavioral;

This VHDL code adds or subtracts two 4-bit unsigned numbers based on the Control input.

Execution Table

Step	A	B	Control	Condition	Operation	Result
1	0011 (3)	0001 (1)	0	Control = '0'?	Add A + B	0100 (4)
2	0101 (5)	0010 (2)	1	Control = '0'?	Subtract A - B	0011 (3)
3	1111 (15)	0001 (1)	0	Control = '0'?	Add A + B	0000 (0) (overflow ignored)
4	0010 (2)	0100 (4)	1	Control = '0'?	Subtract A - B	1110 (14) (underflow, wraps)
5	-	-	-	-	-	End of simulation

💡 Process ends after evaluating inputs and producing output for each case.

Variable Tracker

Variable	Start	After Step 1	After Step 2	After Step 3	After Step 4	Final
A	0000	0011	0101	1111	0010	0010
B	0000	0001	0010	0001	0100	0100
Control	0	0	1	0	1	1
Result	0000	0100	0011	0000	1110	1110

Key Moments - 3 Insights

Why does the result sometimes show a value like 0000 or 1110 after subtraction?

Because the design uses unsigned numbers, subtracting a larger number from a smaller one causes underflow and wraps around, as shown in execution_table rows 3 and 4.

How does the Control signal decide between addition and subtraction?

The Control signal is checked in the process (execution_table column 'Condition'). If it is '0', addition happens; if '1', subtraction happens.

Why is overflow ignored in addition?

The 4-bit unsigned type wraps around on overflow, so the result fits in 4 bits, as seen in execution_table row 3 where 15 + 1 results in 0.

Visual Quiz - 3 Questions

Look at the execution_table at Step 2. What operation is performed and what is the result?

A Subtract A - B, result 3

B Add A + B, result 7

C Add A + B, result 3

D Subtract A - B, result 7

💡 Hint

Check the 'Operation' and 'Result' columns at Step 2 in the execution_table.

At which step does the Control signal equal '0' and the result is 4?

A Step 3

B Step 2

C Step 1

D Step 4

💡 Hint

Look at the Control and Result columns in the execution_table.

If Control is '1' and A=2, B=4, what is the Result according to variable_tracker?

A 6

B 14

C 2

D 4

💡 Hint

See variable_tracker row for Result after Step 4.

Concept Snapshot

VHDL Adder-Subtractor:
Use a Control signal to select operation.
If Control='0', Result = A + B.
If Control='1', Result = A - B.
Unsigned arithmetic wraps on overflow/underflow.
Process sensitive to inputs and Control.

Full Transcript

This VHDL design uses a Control input to decide whether to add or subtract two 4-bit unsigned numbers A and B. When Control is '0', the process adds A and B; when '1', it subtracts B from A. The result is stored in a 4-bit unsigned output. The execution table shows step-by-step how inputs and Control affect the operation and output. Overflow and underflow wrap around due to unsigned arithmetic. The variable tracker records the values of A, B, Control, and Result after each step. Key moments clarify why subtraction can produce wrapped values and how Control directs the operation. The visual quiz tests understanding of these steps and results. This design is a simple example of conditional arithmetic in VHDL.