Adder and subtractor design in VHDL - Step-by-Step Execution

Concept Flow - Adder and subtractor design

Input A, Input B, Control

↓

Check Control

↓

Perform A+B

↓

Output Result

The design checks a control signal to decide whether to add or subtract two inputs, then outputs the result.

Execution Sample

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity AdderSubtractor is
  port(
    A, B : in unsigned(3 downto 0);
    Control : in std_logic; -- 0 for add, 1 for subtract
    Result : out unsigned(3 downto 0)
  );
end entity;

architecture Behavioral of AdderSubtractor is
begin
  process(A, B, Control) is
  begin
    if Control = '0' then
      Result <= A + B;
    else
      Result <= A - B;
    end if;
  end process;
end Behavioral;

This VHDL code adds or subtracts two 4-bit unsigned numbers based on the Control input.

Execution Table

Step	A	B	Control	Condition	Operation	Result
1	0011 (3)	0001 (1)	0	Control = '0'?	Add A + B	0100 (4)
2	0101 (5)	0010 (2)	1	Control = '0'?	Subtract A - B	0011 (3)
3	1111 (15)	0001 (1)	0	Control = '0'?	Add A + B	0000 (0) (overflow ignored)
4	0010 (2)	0100 (4)	1	Control = '0'?	Subtract A - B	1110 (14) (underflow, wraps)
5	-	-	-	-	-	End of simulation

💡 Process ends after evaluating inputs and producing output for each case.

Variable Tracker

Variable	Start	After Step 1	After Step 2	After Step 3	After Step 4	Final
A	0000	0011	0101	1111	0010	0010
B	0000	0001	0010	0001	0100	0100
Control	0	0	1	0	1	1
Result	0000	0100	0011	0000	1110	1110

Key Moments - 3 Insights

Why does the result sometimes show a value like 0000 or 1110 after subtraction?

Because the design uses unsigned numbers, subtracting a larger number from a smaller one causes underflow and wraps around, as shown in execution_table rows 3 and 4.

How does the Control signal decide between addition and subtraction?

The Control signal is checked in the process (execution_table column 'Condition'). If it is '0', addition happens; if '1', subtraction happens.

Why is overflow ignored in addition?

The 4-bit unsigned type wraps around on overflow, so the result fits in 4 bits, as seen in execution_table row 3 where 15 + 1 results in 0.

Visual Quiz - 3 Questions

Look at the execution_table at Step 2. What operation is performed and what is the result?

A Subtract A - B, result 3

B Add A + B, result 7

C Add A + B, result 3

D Subtract A - B, result 7

💡 Hint

Check the 'Operation' and 'Result' columns at Step 2 in the execution_table.

At which step does the Control signal equal '0' and the result is 4?

A Step 3

B Step 2

C Step 1

D Step 4

💡 Hint

Look at the Control and Result columns in the execution_table.

If Control is '1' and A=2, B=4, what is the Result according to variable_tracker?

A 6

B 14

C 2

D 4

💡 Hint

See variable_tracker row for Result after Step 4.

Concept Snapshot

VHDL Adder-Subtractor:
Use a Control signal to select operation.
If Control='0', Result = A + B.
If Control='1', Result = A - B.
Unsigned arithmetic wraps on overflow/underflow.
Process sensitive to inputs and Control.

Full Transcript

This VHDL design uses a Control input to decide whether to add or subtract two 4-bit unsigned numbers A and B. When Control is '0', the process adds A and B; when '1', it subtracts B from A. The result is stored in a 4-bit unsigned output. The execution table shows step-by-step how inputs and Control affect the operation and output. Overflow and underflow wrap around due to unsigned arithmetic. The variable tracker records the values of A, B, Control, and Result after each step. Key moments clarify why subtraction can produce wrapped values and how Control directs the operation. The visual quiz tests understanding of these steps and results. This design is a simple example of conditional arithmetic in VHDL.

Practice

1. What is the main purpose of an adder-subtractor circuit in VHDL?

easy

A. To perform addition or subtraction based on a control signal

B. To multiply two numbers

C. To convert binary to decimal

D. To store data temporarily

Solution

1. Step 1: Understand the function of the circuit

   An adder-subtractor circuit can perform both addition and subtraction operations depending on a control input.

2. Step 2: Identify the correct purpose

   Since the circuit switches between adding and subtracting, its main purpose is to perform addition or subtraction based on a control signal.

3. Final Answer:

   To perform addition or subtraction based on a control signal -> Option A

4. Quick Check:

   Adder-subtractor = add or subtract [OK]

Hint: Adder-subtractor switches operation by control signal [OK]

Common Mistakes:

• Confusing adder-subtractor with multiplier
• Thinking it only adds
• Assuming it stores data

2. Which VHDL type is commonly used to represent binary numbers for arithmetic operations in an adder-subtractor?

easy

A. std_logic_vector

B. integer

C. bit

D. unsigned

Solution

1. Step 1: Identify types for arithmetic

   While std_logic_vector represents bits, it does not support arithmetic directly. The unsigned type allows arithmetic operations on bit vectors.

2. Step 2: Choose the correct type

   For addition and subtraction, unsigned is used to perform arithmetic on bit vectors.

3. Final Answer:

   unsigned -> Option D

4. Quick Check:

   Arithmetic on bits = unsigned type [OK]

Hint: Use unsigned for arithmetic on bit vectors [OK]

Common Mistakes:

• Using std_logic_vector directly for math
• Choosing integer which is not bit vector
• Using bit which is single bit only

3. Given this VHDL snippet for a 4-bit adder-subtractor:

signal A, B : unsigned(3 downto 0);
signal Result : unsigned(3 downto 0);
signal Subtract : std_logic;

Result <= A + (B xor (Subtract & Subtract & Subtract & Subtract)) + Subtract;

What operation does this code perform when Subtract = '1'?

medium

A. Adds A and B

B. Subtracts B from A

C. Performs bitwise AND of A and B

D. Performs bitwise OR of A and B

Solution

1. Step 1: Understand the XOR with Subtract signal

   When Subtract = '1', B is XORed with 1111 (all ones), which flips all bits of B (one's complement).

2. Step 2: Adding Subtract as carry-in

   Adding Subtract ('1') adds 1, completing two's complement of B, so Result = A + two's complement of B = A - B.

3. Final Answer:

   Subtracts B from A -> Option B

4. Quick Check:

   Subtract=1 means add two's complement = subtraction [OK]

Hint: XOR with all ones + 1 = two's complement subtraction [OK]

Common Mistakes:

• Ignoring the carry-in addition
• Thinking XOR flips bits but not adding 1
• Confusing addition with bitwise AND/OR

4. Identify the error in this VHDL code snippet for a subtractor:

Result <= A - B;
-- A and B are std_logic_vector(3 downto 0)

medium

A. Result signal is not declared

B. Missing semicolon after assignment

C. Cannot subtract std_logic_vector directly without conversion

D. Subtraction operator is invalid in VHDL

Solution

1. Step 1: Check types of A and B

   A and B are std_logic_vector, which do not support arithmetic operations directly.

2. Step 2: Identify correct usage

   To subtract, A and B must be converted to unsigned or signed types before subtraction.

3. Final Answer:

   Cannot subtract std_logic_vector directly without conversion -> Option C

4. Quick Check:

   std_logic_vector needs conversion for math [OK]

Hint: Convert std_logic_vector to unsigned before subtracting [OK]

Common Mistakes:

• Trying to subtract std_logic_vector directly
• Ignoring type conversions
• Assuming subtraction operator works on bits

5. You want to design a 4-bit adder-subtractor in VHDL that uses a control signal Sub to select addition (Sub='0') or subtraction (Sub='1'). Which of the following code snippets correctly implements this behavior?

hard

A. Result <= A + (B xor (Sub & Sub & Sub & Sub)) + Sub;

B. Result <= A + B when Sub = '0' else A - B;

C. Result <= A - (B xor (Sub & Sub & Sub & Sub)) - Sub;

D. Result <= A + B xor Sub;

Solution

1. Step 1: Understand two's complement subtraction

   Subtraction is done by adding two's complement of B, which is B XORed with all Sub bits plus Sub as carry-in.

2. Step 2: Analyze each option

   Result <= A + B when Sub = '0' else A - B; uses conditional assignment but does not handle two's complement properly. Result <= A + (B xor (Sub & Sub & Sub & Sub)) + Sub; correctly implements two's complement addition. Result <= A - (B xor (Sub & Sub & Sub & Sub)) - Sub; incorrectly subtracts after XOR. Result <= A + B xor Sub; applies XOR incorrectly.

3. Final Answer:

   Result <= A + (B xor (Sub & Sub & Sub & Sub)) + Sub; -> Option A

4. Quick Check:

   Two's complement subtraction = XOR + carry-in [OK]

Hint: Use XOR with control and add control as carry-in [OK]

Common Mistakes:

• Using conditional without two's complement
• Subtracting instead of adding two's complement
• Misusing XOR without carry-in