Adder and subtractor design in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of 4-bit Adder with Overflow

What is the output and overflow flag of this 4-bit adder when adding A = "1111" and B = "0001"?

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Adder4bit is
    Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
           B : in STD_LOGIC_VECTOR (3 downto 0);
           Sum : out STD_LOGIC_VECTOR (3 downto 0);
           Overflow : out STD_LOGIC);
end Adder4bit;

architecture Behavioral of Adder4bit is
    signal A_int, B_int, Sum_int : signed(3 downto 0);
    signal temp_sum : signed(4 downto 0);
begin
    A_int <= signed(A);
    B_int <= signed(B);
    temp_sum <= ('0' & A_int) + ('0' & B_int);
    Sum_int <= temp_sum(3 downto 0);
    Sum <= std_logic_vector(Sum_int);
    Overflow <= temp_sum(4) xor temp_sum(3);
end Behavioral;

A Sum = "0000", Overflow = '0'

B Sum = "1111", Overflow = '0'

C Sum = "0000", Overflow = '1'

D Sum = "10000", Overflow = '1'

💡 Hint

Remember that overflow occurs when the carry into the sign bit differs from the carry out.

Adding 1111 (-1 in signed 4-bit) and 0001 (+1) results in 0000 (0) with an overflow because the sign bit carry changed.

❓ Predict Output

intermediate

Subtractor Output for 4-bit Inputs

What is the output of this 4-bit subtractor when subtracting B = "0011" from A = "0101"?

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Subtractor4bit is
    Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
           B : in STD_LOGIC_VECTOR (3 downto 0);
           Diff : out STD_LOGIC_VECTOR (3 downto 0);
           Borrow : out STD_LOGIC);
end Subtractor4bit;

architecture Behavioral of Subtractor4bit is
    signal A_int, B_int, Diff_int : unsigned(3 downto 0);
    signal temp_diff : signed(4 downto 0);
begin
    A_int <= unsigned(A);
    B_int <= unsigned(B);
    temp_diff <= signed(('0' & A_int)) - signed(('0' & B_int));
    Diff_int <= unsigned(temp_diff(3 downto 0));
    Diff <= std_logic_vector(Diff_int);
    Borrow <= '1' when temp_diff(4) = '1' else '0';
end Behavioral;

A Diff = "1110", Borrow = '1'

B Diff = "0010", Borrow = '0'

C Diff = "0010", Borrow = '1'

D Diff = "1110", Borrow = '0'

💡 Hint

Borrow is set when the result is negative in unsigned subtraction.

5 - 3 = 2, which fits in 4 bits without borrow, so Diff = 0010 and Borrow = 0.

🔧 Debug

advanced

Identify the Error in 8-bit Adder Design

This VHDL code is intended to add two 8-bit unsigned numbers but produces incorrect results. What is the main error?

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Adder8bit is
    Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
           B : in STD_LOGIC_VECTOR (7 downto 0);
           Sum : out STD_LOGIC_VECTOR (7 downto 0);
           CarryOut : out STD_LOGIC);
end Adder8bit;

architecture Behavioral of Adder8bit is
    signal A_int, B_int : unsigned(7 downto 0);
    signal temp_sum : unsigned(8 downto 0);
begin
    A_int <= unsigned(A);
    B_int <= unsigned(B);
    temp_sum <= ('0' & A_int) + ('0' & B_int);
    Sum <= std_logic_vector(temp_sum(7 downto 0));
    CarryOut <= temp_sum(8);
end Behavioral;

A CarryOut should be assigned temp_sum(7) instead of temp_sum(8).

B temp_sum should be signed type to handle overflow correctly.

C Sum output should be assigned temp_sum(8 downto 1) instead of (7 downto 0).

D temp_sum is declared as unsigned(8 downto 0) but assigned sum of unsigned(7 downto 0) + unsigned(7 downto 0) causing size mismatch.

💡 Hint

Check the size of signals and the result of addition carefully.

Adding two 8-bit unsigned numbers results in a 9-bit sum, so temp_sum must be 9 bits wide. The code declares temp_sum correctly but the addition of A_int + B_int (both 8 bits) returns 8 bits, causing a size mismatch error.

📝 Syntax

advanced

Syntax Error in Subtractor with Borrow

Which option contains the correct syntax to assign the borrow output in this subtractor architecture?

VHDL

Borrow <= '1' when temp_diff(4) = '1' else '0';

A Borrow <= '1' when temp_diff(4) = '1' else '0';

B Borrow := '1' if temp_diff(4) = '1' else '0';

C Borrow = '1' when temp_diff(4) = '1' else '0';

D Borrow <= '1' if temp_diff(4) = '1' else '0';

💡 Hint

Remember VHDL uses '<=' for signal assignment and 'when ... else' for conditional assignment.

Option A uses correct VHDL syntax for conditional signal assignment. Options A, B, and C use invalid syntax for VHDL.

🚀 Application

expert

Design Challenge: Combined Adder-Subtractor Output

Given this VHDL snippet for a combined adder-subtractor, what is the output Sum when A = "0110", B = "0011", and Mode = '1' (subtract)?

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity AddSub4bit is
    Port ( A : in STD_LOGIC_VECTOR(3 downto 0);
           B : in STD_LOGIC_VECTOR(3 downto 0);
           Mode : in STD_LOGIC; -- '0' for add, '1' for subtract
           Sum : out STD_LOGIC_VECTOR(3 downto 0);
           Carry_Borrow : out STD_LOGIC);
end AddSub4bit;

architecture Behavioral of AddSub4bit is
    signal B_mod : STD_LOGIC_VECTOR(3 downto 0);
    signal carry_in : STD_LOGIC;
    signal temp_sum : unsigned(4 downto 0);
begin
    B_mod <= B xor ("1111" when Mode = '1' else "0000");
    carry_in <= Mode;
    temp_sum <= unsigned(('0' & A)) + unsigned(('0' & B_mod)) + to_unsigned(to_integer(unsigned(carry_in & "0000")), 5);
    Sum <= std_logic_vector(temp_sum(3 downto 0));
    Carry_Borrow <= temp_sum(4);
end Behavioral;

A Sum = "0011", Carry_Borrow = '0'

B Sum = "0101", Carry_Borrow = '1'

C Sum = "0011", Carry_Borrow = '1'

D Sum = "0101", Carry_Borrow = '0'

💡 Hint

Subtracting B from A is done by adding A to the two's complement of B.

Mode = '1' means subtract. B_mod is bitwise inverted B (two's complement step), carry_in = 1 adds the +1 for two's complement. 6 - 3 = 3, so Sum = "0011" and Carry_Borrow = '0' (no borrow).