Adder and subtractor design in VHDL - Mini Project: Build & Apply

Adder and Subtractor Design

📖 Scenario: You are designing a simple digital circuit that can add or subtract two 4-bit numbers. This is a common task in digital electronics, used in calculators and computers.

🎯 Goal: Build a VHDL program that defines two 4-bit inputs, a control signal to choose addition or subtraction, and outputs the 4-bit result and a carry/borrow flag.

📋 What You'll Learn

Create two 4-bit input signals named A and B

Create a 1-bit control signal named Sub to select addition (0) or subtraction (1)

Implement the adder and subtractor logic using VHDL

Output the 4-bit result in a signal named Result

Output the carry or borrow flag in a signal named Carry_Borrow

💡 Why This Matters

🌍 Real World

Adder and subtractor circuits are fundamental in digital devices like calculators, computers, and embedded systems to perform arithmetic operations.

💼 Career

Understanding how to design basic arithmetic units in VHDL is essential for hardware engineers working on FPGA or ASIC design.

1

Define the input signals

Create two 4-bit std_logic_vector signals named A and B inside an architecture block.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity AdderSubtractor is
    Port (
        A : in std_logic_vector(3 downto 0);
        B : in std_logic_vector(3 downto 0);
        Sub : in std_logic;
        Result : out std_logic_vector(3 downto 0);
        Carry_Borrow : out std_logic
    );
end AdderSubtractor;

architecture Behavioral of AdderSubtractor is
    -- Your code here
begin

end Behavioral;

Hint

Define A and B as 4-bit input vectors in the entity port.

2

Add the control signal for operation selection

Add a 1-bit std_logic input signal named Sub to the entity port to select addition when Sub = '0' and subtraction when Sub = '1'.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity AdderSubtractor is
    Port (
        A : in std_logic_vector(3 downto 0);
        B : in std_logic_vector(3 downto 0);
        Sub : in std_logic;
        Result : out std_logic_vector(3 downto 0);
        Carry_Borrow : out std_logic
    );
end AdderSubtractor;

architecture Behavioral of AdderSubtractor is
    -- Your code here
begin

end Behavioral;

Hint

Add the Sub signal to the entity port to control addition or subtraction.

3

Implement the adder and subtractor logic

Inside the architecture, create a process that uses the signals A, B, and Sub. Use the expression B_xor = B xor (others => Sub) to invert B when subtracting. Then add A, B_xor, and Sub as carry-in to get a 5-bit sum. Assign the lower 4 bits to Result and the highest bit to Carry_Borrow.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity AdderSubtractor is
    Port (
        A : in std_logic_vector(3 downto 0);
        B : in std_logic_vector(3 downto 0);
        Sub : in std_logic;
        Result : out std_logic_vector(3 downto 0);
        Carry_Borrow : out std_logic
    );
end AdderSubtractor;

architecture Behavioral of AdderSubtractor is
begin
    -- Your code here
end Behavioral;

Hint

Use a process block and the XOR operation on B with Sub to switch between add and subtract. Then add with carry-in Sub.

4

Display the result and carry/borrow flag

Add a print statement inside the process to display the values of A, B, Sub, Result, and Carry_Borrow using report statements for simulation output.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity AdderSubtractor is
    Port (
        A : in std_logic_vector(3 downto 0);
        B : in std_logic_vector(3 downto 0);
        Sub : in std_logic;
        Result : out std_logic_vector(3 downto 0);
        Carry_Borrow : out std_logic
    );
end AdderSubtractor;

architecture Behavioral of AdderSubtractor is
begin
    process(A, B, Sub)
        variable B_xor : std_logic_vector(3 downto 0);
        variable Sum : unsigned(4 downto 0);
    begin
        B_xor := B xor (others => Sub);
        Sum := unsigned(A) + unsigned(B_xor) + unsigned(('0' & Sub)(0));
        Result <= std_logic_vector(Sum(3 downto 0));
        Carry_Borrow <= Sum(4);
        -- Your code here
    end process;
end Behavioral;

Hint

Use report statements to print the values for simulation. Convert vectors to integers for easy reading.

Practice

1. What is the main purpose of an adder-subtractor circuit in VHDL?

easy

A. To perform addition or subtraction based on a control signal

B. To multiply two numbers

C. To convert binary to decimal

D. To store data temporarily

Solution

1. Step 1: Understand the function of the circuit

   An adder-subtractor circuit can perform both addition and subtraction operations depending on a control input.

2. Step 2: Identify the correct purpose

   Since the circuit switches between adding and subtracting, its main purpose is to perform addition or subtraction based on a control signal.

3. Final Answer:

   To perform addition or subtraction based on a control signal -> Option A

4. Quick Check:

   Adder-subtractor = add or subtract [OK]

Hint: Adder-subtractor switches operation by control signal [OK]

Common Mistakes:

• Confusing adder-subtractor with multiplier
• Thinking it only adds
• Assuming it stores data

2. Which VHDL type is commonly used to represent binary numbers for arithmetic operations in an adder-subtractor?

easy

A. std_logic_vector

B. integer

C. bit

D. unsigned

Solution

1. Step 1: Identify types for arithmetic

   While std_logic_vector represents bits, it does not support arithmetic directly. The unsigned type allows arithmetic operations on bit vectors.

2. Step 2: Choose the correct type

   For addition and subtraction, unsigned is used to perform arithmetic on bit vectors.

3. Final Answer:

   unsigned -> Option D

4. Quick Check:

   Arithmetic on bits = unsigned type [OK]

Hint: Use unsigned for arithmetic on bit vectors [OK]

Common Mistakes:

• Using std_logic_vector directly for math
• Choosing integer which is not bit vector
• Using bit which is single bit only

3. Given this VHDL snippet for a 4-bit adder-subtractor:

signal A, B : unsigned(3 downto 0);
signal Result : unsigned(3 downto 0);
signal Subtract : std_logic;

Result <= A + (B xor (Subtract & Subtract & Subtract & Subtract)) + Subtract;

What operation does this code perform when Subtract = '1'?

medium

A. Adds A and B

B. Subtracts B from A

C. Performs bitwise AND of A and B

D. Performs bitwise OR of A and B

Solution

1. Step 1: Understand the XOR with Subtract signal

   When Subtract = '1', B is XORed with 1111 (all ones), which flips all bits of B (one's complement).

2. Step 2: Adding Subtract as carry-in

   Adding Subtract ('1') adds 1, completing two's complement of B, so Result = A + two's complement of B = A - B.

3. Final Answer:

   Subtracts B from A -> Option B

4. Quick Check:

   Subtract=1 means add two's complement = subtraction [OK]

Hint: XOR with all ones + 1 = two's complement subtraction [OK]

Common Mistakes:

• Ignoring the carry-in addition
• Thinking XOR flips bits but not adding 1
• Confusing addition with bitwise AND/OR

4. Identify the error in this VHDL code snippet for a subtractor:

Result <= A - B;
-- A and B are std_logic_vector(3 downto 0)

medium

A. Result signal is not declared

B. Missing semicolon after assignment

C. Cannot subtract std_logic_vector directly without conversion

D. Subtraction operator is invalid in VHDL

Solution

1. Step 1: Check types of A and B

   A and B are std_logic_vector, which do not support arithmetic operations directly.

2. Step 2: Identify correct usage

   To subtract, A and B must be converted to unsigned or signed types before subtraction.

3. Final Answer:

   Cannot subtract std_logic_vector directly without conversion -> Option C

4. Quick Check:

   std_logic_vector needs conversion for math [OK]

Hint: Convert std_logic_vector to unsigned before subtracting [OK]

Common Mistakes:

• Trying to subtract std_logic_vector directly
• Ignoring type conversions
• Assuming subtraction operator works on bits

5. You want to design a 4-bit adder-subtractor in VHDL that uses a control signal Sub to select addition (Sub='0') or subtraction (Sub='1'). Which of the following code snippets correctly implements this behavior?

hard

A. Result <= A + (B xor (Sub & Sub & Sub & Sub)) + Sub;

B. Result <= A + B when Sub = '0' else A - B;

C. Result <= A - (B xor (Sub & Sub & Sub & Sub)) - Sub;

D. Result <= A + B xor Sub;

Solution

1. Step 1: Understand two's complement subtraction

   Subtraction is done by adding two's complement of B, which is B XORed with all Sub bits plus Sub as carry-in.

2. Step 2: Analyze each option

   Result <= A + B when Sub = '0' else A - B; uses conditional assignment but does not handle two's complement properly. Result <= A + (B xor (Sub & Sub & Sub & Sub)) + Sub; correctly implements two's complement addition. Result <= A - (B xor (Sub & Sub & Sub & Sub)) - Sub; incorrectly subtracts after XOR. Result <= A + B xor Sub; applies XOR incorrectly.

3. Final Answer:

   Result <= A + (B xor (Sub & Sub & Sub & Sub)) + Sub; -> Option A

4. Quick Check:

   Two's complement subtraction = XOR + carry-in [OK]

Hint: Use XOR with control and add control as carry-in [OK]

Common Mistakes:

• Using conditional without two's complement
• Subtracting instead of adding two's complement
• Misusing XOR without carry-in