Adder and subtractor design in VHDL - Mini Project: Build & Apply

Adder and Subtractor Design

📖 Scenario: You are designing a simple digital circuit that can add or subtract two 4-bit numbers. This is a common task in digital electronics, used in calculators and computers.

🎯 Goal: Build a VHDL program that defines two 4-bit inputs, a control signal to choose addition or subtraction, and outputs the 4-bit result and a carry/borrow flag.

📋 What You'll Learn

Create two 4-bit input signals named A and B

Create a 1-bit control signal named Sub to select addition (0) or subtraction (1)

Implement the adder and subtractor logic using VHDL

Output the 4-bit result in a signal named Result

Output the carry or borrow flag in a signal named Carry_Borrow

💡 Why This Matters

🌍 Real World

Adder and subtractor circuits are fundamental in digital devices like calculators, computers, and embedded systems to perform arithmetic operations.

💼 Career

Understanding how to design basic arithmetic units in VHDL is essential for hardware engineers working on FPGA or ASIC design.

1

Define the input signals

Create two 4-bit std_logic_vector signals named A and B inside an architecture block.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity AdderSubtractor is
    Port (
        A : in std_logic_vector(3 downto 0);
        B : in std_logic_vector(3 downto 0);
        Sub : in std_logic;
        Result : out std_logic_vector(3 downto 0);
        Carry_Borrow : out std_logic
    );
end AdderSubtractor;

architecture Behavioral of AdderSubtractor is
    -- Your code here
begin

end Behavioral;

Need a hint?

Define A and B as 4-bit input vectors in the entity port.

2

Add the control signal for operation selection

Add a 1-bit std_logic input signal named Sub to the entity port to select addition when Sub = '0' and subtraction when Sub = '1'.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity AdderSubtractor is
    Port (
        A : in std_logic_vector(3 downto 0);
        B : in std_logic_vector(3 downto 0);
        Sub : in std_logic;
        Result : out std_logic_vector(3 downto 0);
        Carry_Borrow : out std_logic
    );
end AdderSubtractor;

architecture Behavioral of AdderSubtractor is
    -- Your code here
begin

end Behavioral;

Need a hint?

Add the Sub signal to the entity port to control addition or subtraction.

3

Implement the adder and subtractor logic

Inside the architecture, create a process that uses the signals A, B, and Sub. Use the expression B_xor = B xor (others => Sub) to invert B when subtracting. Then add A, B_xor, and Sub as carry-in to get a 5-bit sum. Assign the lower 4 bits to Result and the highest bit to Carry_Borrow.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity AdderSubtractor is
    Port (
        A : in std_logic_vector(3 downto 0);
        B : in std_logic_vector(3 downto 0);
        Sub : in std_logic;
        Result : out std_logic_vector(3 downto 0);
        Carry_Borrow : out std_logic
    );
end AdderSubtractor;

architecture Behavioral of AdderSubtractor is
begin
    -- Your code here
end Behavioral;

Need a hint?

Use a process block and the XOR operation on B with Sub to switch between add and subtract. Then add with carry-in Sub.

4

Display the result and carry/borrow flag

Add a print statement inside the process to display the values of A, B, Sub, Result, and Carry_Borrow using report statements for simulation output.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity AdderSubtractor is
    Port (
        A : in std_logic_vector(3 downto 0);
        B : in std_logic_vector(3 downto 0);
        Sub : in std_logic;
        Result : out std_logic_vector(3 downto 0);
        Carry_Borrow : out std_logic
    );
end AdderSubtractor;

architecture Behavioral of AdderSubtractor is
begin
    process(A, B, Sub)
        variable B_xor : std_logic_vector(3 downto 0);
        variable Sum : unsigned(4 downto 0);
    begin
        B_xor := B xor (others => Sub);
        Sum := unsigned(A) + unsigned(B_xor) + unsigned(('0' & Sub)(0));
        Result <= std_logic_vector(Sum(3 downto 0));
        Carry_Borrow <= Sum(4);
        -- Your code here
    end process;
end Behavioral;

Need a hint?

Use report statements to print the values for simulation. Convert vectors to integers for easy reading.