Adder and subtractor design in VHDL - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a 4-bit input signal named 'A'.

VHDL

signal A : std_logic_vector([1] downto 0);

Drag options to blanks, or click blank then click option'

A7

B4

C3

D1

Attempts:

3 left

💡 Hint

Common Mistakes

Using 4 as the highest index instead of 3.

Confusing the direction of the range (downto vs to).

The signal 'A' is declared as a 4-bit vector, so the highest index is 3 (0 to 3).

2fill in blank

medium

Complete the code to perform addition of two 4-bit vectors A and B and assign the result to SUM.

VHDL

SUM <= std_logic_vector(unsigned(A) [1] unsigned(B));

Drag options to blanks, or click blank then click option'

A+

B*

C&

D-

Attempts:

3 left

💡 Hint

Common Mistakes

Using '-' which subtracts instead of adds.

Using '&' which concatenates vectors.

The '+' operator is used to add two unsigned vectors in VHDL.

3fill in blank

hard

Fix the error in the subtraction operation between A and B.

VHDL

DIFF <= std_logic_vector(unsigned(A) [1] unsigned(B));

Drag options to blanks, or click blank then click option'

A-

B/

C*

D+

Attempts:

3 left

💡 Hint

Common Mistakes

Using '+' which adds instead of subtracts.

Using '*' which multiplies instead of subtracts.

The '-' operator correctly subtracts unsigned vectors in VHDL.

4fill in blank

hard

Fill both blanks to create a process sensitive to inputs A and B.

VHDL

process([1], [2])
begin
  -- process body
end process;

Drag options to blanks, or click blank then click option'

AA

BCLK

CB

DRESET

Attempts:

3 left

💡 Hint

Common Mistakes

Including CLK or RESET which are unrelated here.

Leaving the sensitivity list empty.

The process should be sensitive to inputs A and B to react when they change.

5fill in blank

hard

Fill all three blanks to assign the subtraction result to DIFF with proper type conversion.

VHDL

DIFF <= std_logic_vector([1](A) [2] [3](B));

Drag options to blanks, or click blank then click option'

Aunsigned

B-

Dsigned

Attempts:

3 left

💡 Hint

Common Mistakes

Mixing 'signed' and 'unsigned' types.

Using '+' instead of '-' for subtraction.

Both A and B are converted to unsigned before subtraction with '-'. The result is then converted back to std_logic_vector.

Practice

1. What is the main purpose of an adder-subtractor circuit in VHDL?

easy

A. To perform addition or subtraction based on a control signal

B. To multiply two numbers

C. To convert binary to decimal

D. To store data temporarily

Solution

1. Step 1: Understand the function of the circuit

   An adder-subtractor circuit can perform both addition and subtraction operations depending on a control input.

2. Step 2: Identify the correct purpose

   Since the circuit switches between adding and subtracting, its main purpose is to perform addition or subtraction based on a control signal.

3. Final Answer:

   To perform addition or subtraction based on a control signal -> Option A

4. Quick Check:

   Adder-subtractor = add or subtract [OK]

Hint: Adder-subtractor switches operation by control signal [OK]

Common Mistakes:

• Confusing adder-subtractor with multiplier
• Thinking it only adds
• Assuming it stores data

2. Which VHDL type is commonly used to represent binary numbers for arithmetic operations in an adder-subtractor?

easy

A. std_logic_vector

B. integer

C. bit

D. unsigned

Solution

1. Step 1: Identify types for arithmetic

   While std_logic_vector represents bits, it does not support arithmetic directly. The unsigned type allows arithmetic operations on bit vectors.

2. Step 2: Choose the correct type

   For addition and subtraction, unsigned is used to perform arithmetic on bit vectors.

3. Final Answer:

   unsigned -> Option D

4. Quick Check:

   Arithmetic on bits = unsigned type [OK]

Hint: Use unsigned for arithmetic on bit vectors [OK]

Common Mistakes:

• Using std_logic_vector directly for math
• Choosing integer which is not bit vector
• Using bit which is single bit only

3. Given this VHDL snippet for a 4-bit adder-subtractor:

signal A, B : unsigned(3 downto 0);
signal Result : unsigned(3 downto 0);
signal Subtract : std_logic;

Result <= A + (B xor (Subtract & Subtract & Subtract & Subtract)) + Subtract;

What operation does this code perform when Subtract = '1'?

medium

A. Adds A and B

B. Subtracts B from A

C. Performs bitwise AND of A and B

D. Performs bitwise OR of A and B

Solution

1. Step 1: Understand the XOR with Subtract signal

   When Subtract = '1', B is XORed with 1111 (all ones), which flips all bits of B (one's complement).

2. Step 2: Adding Subtract as carry-in

   Adding Subtract ('1') adds 1, completing two's complement of B, so Result = A + two's complement of B = A - B.

3. Final Answer:

   Subtracts B from A -> Option B

4. Quick Check:

   Subtract=1 means add two's complement = subtraction [OK]

Hint: XOR with all ones + 1 = two's complement subtraction [OK]

Common Mistakes:

• Ignoring the carry-in addition
• Thinking XOR flips bits but not adding 1
• Confusing addition with bitwise AND/OR

4. Identify the error in this VHDL code snippet for a subtractor:

Result <= A - B;
-- A and B are std_logic_vector(3 downto 0)

medium

A. Result signal is not declared

B. Missing semicolon after assignment

C. Cannot subtract std_logic_vector directly without conversion

D. Subtraction operator is invalid in VHDL

Solution

1. Step 1: Check types of A and B

   A and B are std_logic_vector, which do not support arithmetic operations directly.

2. Step 2: Identify correct usage

   To subtract, A and B must be converted to unsigned or signed types before subtraction.

3. Final Answer:

   Cannot subtract std_logic_vector directly without conversion -> Option C

4. Quick Check:

   std_logic_vector needs conversion for math [OK]

Hint: Convert std_logic_vector to unsigned before subtracting [OK]

Common Mistakes:

• Trying to subtract std_logic_vector directly
• Ignoring type conversions
• Assuming subtraction operator works on bits

5. You want to design a 4-bit adder-subtractor in VHDL that uses a control signal Sub to select addition (Sub='0') or subtraction (Sub='1'). Which of the following code snippets correctly implements this behavior?

hard

A. Result <= A + (B xor (Sub & Sub & Sub & Sub)) + Sub;

B. Result <= A + B when Sub = '0' else A - B;

C. Result <= A - (B xor (Sub & Sub & Sub & Sub)) - Sub;

D. Result <= A + B xor Sub;

Solution

1. Step 1: Understand two's complement subtraction

   Subtraction is done by adding two's complement of B, which is B XORed with all Sub bits plus Sub as carry-in.

2. Step 2: Analyze each option

   Result <= A + B when Sub = '0' else A - B; uses conditional assignment but does not handle two's complement properly. Result <= A + (B xor (Sub & Sub & Sub & Sub)) + Sub; correctly implements two's complement addition. Result <= A - (B xor (Sub & Sub & Sub & Sub)) - Sub; incorrectly subtracts after XOR. Result <= A + B xor Sub; applies XOR incorrectly.

3. Final Answer:

   Result <= A + (B xor (Sub & Sub & Sub & Sub)) + Sub; -> Option A

4. Quick Check:

   Two's complement subtraction = XOR + carry-in [OK]

Hint: Use XOR with control and add control as carry-in [OK]

Common Mistakes:

• Using conditional without two's complement
• Subtracting instead of adding two's complement
• Misusing XOR without carry-in