Adder and subtractor design in VHDL - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a 4-bit input signal named 'A'.

VHDL

signal A : std_logic_vector([1] downto 0);

Drag options to blanks, or click blank then click option'

A7

B4

C3

D1

Attempts:

3 left

💡 Hint

Common Mistakes

Using 4 as the highest index instead of 3.

Confusing the direction of the range (downto vs to).

The signal 'A' is declared as a 4-bit vector, so the highest index is 3 (0 to 3).

2fill in blank

medium

Complete the code to perform addition of two 4-bit vectors A and B and assign the result to SUM.

VHDL

SUM <= std_logic_vector(unsigned(A) [1] unsigned(B));

Drag options to blanks, or click blank then click option'

A+

B*

C&

D-

Attempts:

3 left

💡 Hint

Common Mistakes

Using '-' which subtracts instead of adds.

Using '&' which concatenates vectors.

The '+' operator is used to add two unsigned vectors in VHDL.

3fill in blank

hard

Fix the error in the subtraction operation between A and B.

VHDL

DIFF <= std_logic_vector(unsigned(A) [1] unsigned(B));

Drag options to blanks, or click blank then click option'

A-

B/

C*

D+

Attempts:

3 left

💡 Hint

Common Mistakes

Using '+' which adds instead of subtracts.

Using '*' which multiplies instead of subtracts.

The '-' operator correctly subtracts unsigned vectors in VHDL.

4fill in blank

hard

Fill both blanks to create a process sensitive to inputs A and B.

VHDL

process([1], [2])
begin
  -- process body
end process;

Drag options to blanks, or click blank then click option'

AA

BCLK

CB

DRESET

Attempts:

3 left

💡 Hint

Common Mistakes

Including CLK or RESET which are unrelated here.

Leaving the sensitivity list empty.

The process should be sensitive to inputs A and B to react when they change.

5fill in blank

hard

Fill all three blanks to assign the subtraction result to DIFF with proper type conversion.

VHDL

DIFF <= std_logic_vector([1](A) [2] [3](B));

Drag options to blanks, or click blank then click option'

Aunsigned

B-

Dsigned

Attempts:

3 left

💡 Hint

Common Mistakes

Mixing 'signed' and 'unsigned' types.

Using '+' instead of '-' for subtraction.

Both A and B are converted to unsigned before subtraction with '-'. The result is then converted back to std_logic_vector.