Signal assignment operator in VHDL - Step-by-Step Execution

Concept Flow - Signal assignment operator

Signal declared

↓

Signal assigned value with <=

↓

Signal update scheduled

↓

After delta delay, signal value changes

↓

Process or architecture sees new signal value

In VHDL, the signal assignment operator '<=' schedules a signal to update its value after a small delay, not immediately.

Execution Sample

VHDL

signal a : std_logic := '0';

process
begin
  a <= '1';
  wait for 10 ns;
end process;

This code assigns '1' to signal 'a' using '<=', which updates 'a' after a delta delay, then waits 10 ns.

Execution Table

Step	Signal 'a' Current Value	Action	Scheduled Update	Signal 'a' Value After Update
1	'0'	Initial value of signal 'a'	None	'0'
2	'0'	Assign '1' to 'a' with '<='	Schedule 'a' = '1' after delta delay	'0'
3	'0'	Delta delay passes, update signal 'a'	None	'1'
4	'1'	Wait for 10 ns (signal stable)	None	'1'

💡 Signal 'a' updates to '1' after delta delay; process waits 10 ns with 'a' = '1'

Variable Tracker

Signal 'a'	Start	After Assignment	After Delta Delay	Final
a	'0'	'0' (scheduled '1')	'1'	'1'

Key Moments - 2 Insights

Why doesn't signal 'a' change immediately after the assignment with '<='?

Because '<=' schedules the update after a delta delay, so in step 2 'a' is still '0' until step 3 when the update happens.

What is the difference between signal assignment '<=' and variable assignment ':=' in VHDL?

Signal assignment '<=' schedules an update after delta delay (see execution_table step 2 and 3), while variable assignment ':=' updates immediately within the process.

Visual Quiz - 3 Questions

Look at the execution table, what is the value of signal 'a' immediately after the assignment in step 2?

A '0'

B '1'

C Undefined

D Signal 'a' is removed

💡 Hint

Check the 'Signal 'a' Current Value' and 'Signal 'a' Value After Update' columns in step 2.

At which step does signal 'a' actually change to '1'?

A Step 1

B Step 2

C Step 3

D Step 4

💡 Hint

Look for when the scheduled update is applied in the execution_table.

If we replaced '<=' with ':=' for signal 'a', how would the value change after assignment?

A Signal 'a' would never update

B Signal 'a' would update immediately

C Signal 'a' would update after 10 ns

D Signal 'a' would update after delta delay

💡 Hint

Recall the difference between signal '<=' and variable ':=' assignments explained in key moments.

Concept Snapshot

Signal assignment operator '<=' in VHDL:
- Assigns a new value to a signal
- Update happens after a delta delay, not immediately
- Used to model hardware signal changes
- Different from variable ':=' which updates immediately
- Important for correct simulation timing

Full Transcript

In VHDL, signals represent hardware wires or registers. When you assign a value to a signal using the '<=' operator, the change does not happen right away. Instead, the new value is scheduled to take effect after a very small delay called a delta delay. This means that immediately after the assignment, the signal still holds its old value. After the delta delay passes, the signal updates to the new value. This behavior is different from variables in VHDL, which update immediately when assigned with ':='. Understanding this timing is important to correctly simulate hardware behavior. The example code shows a signal 'a' starting at '0', then assigned '1' with '<='. The signal 'a' remains '0' right after assignment, then changes to '1' after the delta delay, before the process waits 10 nanoseconds.