Signal assignment operator in VHDL - Step-by-Step Execution

Concept Flow - Signal assignment operator

Signal declared

↓

Signal assigned value with <=

↓

Signal update scheduled

↓

After delta delay, signal value changes

↓

Process or architecture sees new signal value

In VHDL, the signal assignment operator '<=' schedules a signal to update its value after a small delay, not immediately.

Execution Sample

VHDL

signal a : std_logic := '0';

process
begin
  a <= '1';
  wait for 10 ns;
end process;

This code assigns '1' to signal 'a' using '<=', which updates 'a' after a delta delay, then waits 10 ns.

Execution Table

Step	Signal 'a' Current Value	Action	Scheduled Update	Signal 'a' Value After Update
1	'0'	Initial value of signal 'a'	None	'0'
2	'0'	Assign '1' to 'a' with '<='	Schedule 'a' = '1' after delta delay	'0'
3	'0'	Delta delay passes, update signal 'a'	None	'1'
4	'1'	Wait for 10 ns (signal stable)	None	'1'

💡 Signal 'a' updates to '1' after delta delay; process waits 10 ns with 'a' = '1'

Variable Tracker

Signal 'a'	Start	After Assignment	After Delta Delay	Final
a	'0'	'0' (scheduled '1')	'1'	'1'

Key Moments - 2 Insights

Why doesn't signal 'a' change immediately after the assignment with '<='?

Because '<=' schedules the update after a delta delay, so in step 2 'a' is still '0' until step 3 when the update happens.

What is the difference between signal assignment '<=' and variable assignment ':=' in VHDL?

Signal assignment '<=' schedules an update after delta delay (see execution_table step 2 and 3), while variable assignment ':=' updates immediately within the process.

Visual Quiz - 3 Questions

Look at the execution table, what is the value of signal 'a' immediately after the assignment in step 2?

A '0'

B '1'

C Undefined

D Signal 'a' is removed

💡 Hint

Check the 'Signal 'a' Current Value' and 'Signal 'a' Value After Update' columns in step 2.

At which step does signal 'a' actually change to '1'?

A Step 1

B Step 2

C Step 3

D Step 4

💡 Hint

Look for when the scheduled update is applied in the execution_table.

If we replaced '<=' with ':=' for signal 'a', how would the value change after assignment?

A Signal 'a' would never update

B Signal 'a' would update immediately

C Signal 'a' would update after 10 ns

D Signal 'a' would update after delta delay

💡 Hint

Recall the difference between signal '<=' and variable ':=' assignments explained in key moments.

Concept Snapshot

Signal assignment operator '<=' in VHDL:
- Assigns a new value to a signal
- Update happens after a delta delay, not immediately
- Used to model hardware signal changes
- Different from variable ':=' which updates immediately
- Important for correct simulation timing

Full Transcript

In VHDL, signals represent hardware wires or registers. When you assign a value to a signal using the '<=' operator, the change does not happen right away. Instead, the new value is scheduled to take effect after a very small delay called a delta delay. This means that immediately after the assignment, the signal still holds its old value. After the delta delay passes, the signal updates to the new value. This behavior is different from variables in VHDL, which update immediately when assigned with ':='. Understanding this timing is important to correctly simulate hardware behavior. The example code shows a signal 'a' starting at '0', then assigned '1' with '<='. The signal 'a' remains '0' right after assignment, then changes to '1' after the delta delay, before the process waits 10 nanoseconds.

Practice

1. What does the signal assignment operator <= do in VHDL?

easy

A. It compares two signals for equality.

B. It immediately changes the value of a variable.

C. It assigns a new value to a signal after the current process finishes.

D. It declares a new signal in the architecture.

Solution

1. Step 1: Understand signal assignment in VHDL

   The operator <= is used to assign values to signals, not variables.

2. Step 2: Timing of assignment

   Signal assignments take effect after the process completes, not instantly.

3. Final Answer:

   It assigns a new value to a signal after the current process finishes. -> Option C

4. Quick Check:

   Signal assignment = delayed update [OK]

Hint: Signal assignments update after process ends, not instantly [OK]

Common Mistakes:

• Confusing signal assignment with variable assignment
• Thinking signal changes happen immediately
• Using = instead of <= for signals

2. Which of the following is the correct syntax to assign the value '1' to a signal named clk in VHDL?

easy

A. clk <= '1';

B. clk == '1';

C. clk := '1';

D. clk = '1';

Solution

1. Step 1: Identify correct assignment operator for signals

   In VHDL, signals use <= for assignment, not = or :=.

2. Step 2: Check syntax correctness

   The correct syntax is clk <= '1'; with single quotes for bit values.

3. Final Answer:

   clk <= '1'; -> Option A

4. Quick Check:

   Signal assignment uses <= [OK]

Hint: Use <= for signals, := for variables [OK]

Common Mistakes:

• Using = instead of <= for signals
• Using := which is for variables
• Using double equals == which is invalid in VHDL

3. Consider the following VHDL process:

process(clk)
begin
  if rising_edge(clk) then
    signal_a <= '1';
    signal_b <= signal_a;
  end if;
end process;

What will be the value of signal_b after the rising edge of clk?

medium

A. The previous value of signal_a

B. '0'

C. '1'

D. Undefined (error)

Solution

1. Step 1: Understand signal assignment timing

   Signal assignments happen after the process finishes, so signal_a updates only after the process.

2. Step 2: Analyze signal_b assignment

   signal_b is assigned the current value of signal_a, which is still the old value during this process.

3. Final Answer:

   The previous value of signal_a -> Option A

4. Quick Check:

   Signal update delayed, so signal_b gets old signal_a [OK]

Hint: Signal updates happen after process, so use old values inside process [OK]

Common Mistakes:

• Assuming signal_a updates immediately
• Confusing signals with variables
• Expecting signal_b to get new signal_a value instantly

4. Identify the error in the following VHDL code snippet:

process(clk)
begin
  if rising_edge(clk) then
    signal_x = '0';
  end if;
end process;

medium

A. Signal signal_x is not declared.

B. Missing semicolon after rising_edge(clk).

C. Process sensitivity list is incorrect.

D. Using = instead of <= for signal assignment.

Solution

1. Step 1: Check assignment operator used

   The code uses = to assign a value to a signal, which is incorrect in VHDL.

2. Step 2: Correct operator for signals

   Signal assignments must use <= operator.

3. Final Answer:

   Using = instead of <= for signal assignment. -> Option D

4. Quick Check:

   Signal assignment requires <= [OK]

Hint: Signals use <=, variables use := [OK]

Common Mistakes:

• Using = instead of <= for signals
• Confusing process sensitivity list
• Assuming missing semicolon causes error

5. You want to create a VHDL process that toggles a signal toggle_sig every clock cycle. Which of the following code snippets correctly uses the signal assignment operator to achieve this?

hard

A. process(clk)
begin
if rising_edge(clk) then
toggle_sig = not toggle_sig;
end if;
end process;

B. process(clk)
begin
if rising_edge(clk) then
toggle_sig <= not toggle_sig;
end if;
end process;

C. process(clk)
begin
if rising_edge(clk) then
toggle_sig := not toggle_sig;
end if;
end process;

D. process(clk)
begin
if rising_edge(clk) then
toggle_sig <= toggle_sig;
end if;
end process;

Solution

1. Step 1: Identify correct signal assignment operator

   In VHDL, signals use <= for assignment, not = or :=.

2. Step 2: Check logic for toggling signal

   Using toggle_sig <= not toggle_sig; correctly flips the signal each clock cycle.

3. Step 3: Eliminate incorrect options

   Using = or := is incorrect for signals. Assigning toggle_sig <= toggle_sig; keeps the same value, no toggle.

4. Final Answer:

   process(clk) begin if rising_edge(clk) then toggle_sig <= not toggle_sig; end if; end process; -> Option B

5. Quick Check:

   Use <= and invert signal to toggle [OK]

Hint: Toggle with <= and not operator inside clocked process [OK]

Common Mistakes:

• Using = or := instead of <= for signals
• Assigning signal to itself without change
• Forgetting to use rising_edge(clk)