Signal assignment operator in VHDL - Mini Project: Build & Apply

Signal Assignment Operator in VHDL

📖 Scenario: You are designing a simple digital circuit that controls an LED light. The LED should turn on or off based on a switch input. You will use VHDL to describe this behavior.

🎯 Goal: Create a VHDL design that uses the signal assignment operator ( to assign the switch input value to the LED output signal.

📋 What You'll Learn

Create a signal called switch of type std_logic.

Create a signal called led of type std_logic.

Assign the value of switch to led using the signal assignment operator <=.

Print the value of led in a process to simulate output.

💡 Why This Matters

🌍 Real World

Signal assignment is fundamental in digital circuit design to control outputs based on inputs, such as turning LEDs on or off.

💼 Career

Understanding signal assignment in VHDL is essential for hardware engineers and FPGA developers who design and simulate digital circuits.

1

Create signals for switch and led

Create two signals called switch and led of type std_logic inside the architecture.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity LED_Control is
    Port ();
end LED_Control;

architecture Behavioral of LED_Control is
    -- Declare signals here
    -- Your code here
begin

end Behavioral;

Need a hint?

Use signal keyword to declare signals inside the architecture before begin.

2

Initialize the switch signal

Assign the value '1' to the signal switch inside the architecture before begin using the signal assignment operator <=.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity LED_Control is
    Port ();
end LED_Control;

architecture Behavioral of LED_Control is
    signal switch : std_logic;
    signal led : std_logic;
    -- Initialize switch signal here
    -- Your code here
begin

end Behavioral;

Need a hint?

Use := '1' to set the initial value of the signal switch.

3

Assign switch value to led using signal assignment operator

Use the signal assignment operator <= to assign the value of switch to led inside the architecture body after begin.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity LED_Control is
    Port ();
end LED_Control;

architecture Behavioral of LED_Control is
    signal switch : std_logic := '1';
    signal led : std_logic;
begin
    -- Assign switch to led here
    -- Your code here
end Behavioral;

Need a hint?

Use led <= switch; after begin to assign the signal.

4

Print the led signal value in a process

Create a process that prints the value of led using report statement inside the architecture body after the signal assignment.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity LED_Control is
    Port ();
end LED_Control;

architecture Behavioral of LED_Control is
    signal switch : std_logic := '1';
    signal led : std_logic;
begin
    led <= switch;
    -- Add a process to report led value
    -- Your code here
end Behavioral;

Need a hint?

Use a process with report and std_logic'image(led) to print the signal value.