Signal assignment operator in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output of this VHDL process with signal assignment?

Consider the following VHDL process. What will be the value of signal_out after the process executes once?

VHDL

signal signal_out : std_logic := '0';
begin
  process
  begin
    signal_out <= '1';
    wait for 10 ns;
  end process;

A signal_out = '0' immediately after process starts

B signal_out = '1' immediately after process starts

C signal_out = '1' after 10 ns delay

D signal_out remains '0' forever

💡 Hint

Remember that signal assignments in VHDL take effect after the process suspends.

Signal assignments in VHDL do not update the signal immediately. The new value is scheduled and takes effect after the process suspends or after delta cycles. Here, signal_out will change to '1' upon process suspension (in the next delta cycle).

❓ Predict Output

intermediate

What is the output of multiple signal assignments in one process?

Given this VHDL process, what will be the final value of sig after the process runs?

VHDL

signal sig : std_logic := '0';
begin
  process
  begin
    sig <= '1';
    sig <= '0';
    wait for 5 ns;
  end process;

A sig = '1' immediately

B sig = '1' after 5 ns

C sig = '0' after 5 ns

D sig = '0' immediately

💡 Hint

Later signal assignments override earlier ones within the same process execution.

Within a single process execution, the last signal assignment determines the final value. Here, sig is assigned '1' then '0', so it will be '0' after the process suspends (after 5 ns).

🔧 Debug

advanced

Identify the error in this signal assignment code

What error will this VHDL code produce?

VHDL

signal a : std_logic := '0';
begin
  process
  begin
    a = '1';
    wait for 10 ns;
  end process;

A Syntax error: missing semicolon after assignment

B Runtime error: signal 'a' not initialized

C No error, code runs fine

D Syntax error: '=' used instead of '<=' for signal assignment

💡 Hint

Check the correct operator for signal assignment in VHDL.

In VHDL, signals are assigned using the '<=' operator, not '=' which is used for variables or comparisons.

🧠 Conceptual

advanced

How does signal assignment timing affect simulation?

Which statement best describes when a signal assignment takes effect in VHDL?

A Signal assignments take effect after the process suspends and delta cycles complete

B Signal assignments take effect immediately when executed in the process

C Signal assignments take effect only after the entire simulation cycle ends

D Signal assignments take effect only if the signal is a variable

💡 Hint

Think about how VHDL schedules signal updates.

Signal assignments in VHDL are scheduled and take effect after the process suspends and all delta cycles are processed, not immediately.

🚀 Application

expert

Determine the final signal value after multiple processes assign it

Given two concurrent processes assigning to the same signal sig, what is the final value of sig after 20 ns?

VHDL

signal sig : std_logic := '0';

process_1: process
begin
  wait for 10 ns;
  sig <= '1';
  wait;
end process;

process_2: process
begin
  wait for 15 ns;
  sig <= '0';
  wait;
end process;

A sig = 'X' (driver conflict) after 20 ns

B sig = '1' after 20 ns

C sig = '0' after 20 ns

D sig = 'Z' (high impedance) after 20 ns

💡 Hint

Consider the order of signal assignments, their timing, and std_logic resolution with multiple drivers.

At 10 ns, process_1 assigns '1' (second driver undriven, equivalent to 'Z'; resolved to '1'). At 15 ns, process_2 assigns '0' (drivers now '1' and '0'; std_logic resolves to 'X'). After 20 ns, remains 'X'.

Practice

1. What does the signal assignment operator <= do in VHDL?

easy

A. It compares two signals for equality.

B. It immediately changes the value of a variable.

C. It assigns a new value to a signal after the current process finishes.

D. It declares a new signal in the architecture.

Solution

1. Step 1: Understand signal assignment in VHDL

   The operator <= is used to assign values to signals, not variables.

2. Step 2: Timing of assignment

   Signal assignments take effect after the process completes, not instantly.

3. Final Answer:

   It assigns a new value to a signal after the current process finishes. -> Option C

4. Quick Check:

   Signal assignment = delayed update [OK]

Hint: Signal assignments update after process ends, not instantly [OK]

Common Mistakes:

• Confusing signal assignment with variable assignment
• Thinking signal changes happen immediately
• Using = instead of <= for signals

2. Which of the following is the correct syntax to assign the value '1' to a signal named clk in VHDL?

easy

A. clk <= '1';

B. clk == '1';

C. clk := '1';

D. clk = '1';

Solution

1. Step 1: Identify correct assignment operator for signals

   In VHDL, signals use <= for assignment, not = or :=.

2. Step 2: Check syntax correctness

   The correct syntax is clk <= '1'; with single quotes for bit values.

3. Final Answer:

   clk <= '1'; -> Option A

4. Quick Check:

   Signal assignment uses <= [OK]

Hint: Use <= for signals, := for variables [OK]

Common Mistakes:

• Using = instead of <= for signals
• Using := which is for variables
• Using double equals == which is invalid in VHDL

3. Consider the following VHDL process:

process(clk)
begin
  if rising_edge(clk) then
    signal_a <= '1';
    signal_b <= signal_a;
  end if;
end process;

What will be the value of signal_b after the rising edge of clk?

medium

A. The previous value of signal_a

B. '0'

C. '1'

D. Undefined (error)

Solution

1. Step 1: Understand signal assignment timing

   Signal assignments happen after the process finishes, so signal_a updates only after the process.

2. Step 2: Analyze signal_b assignment

   signal_b is assigned the current value of signal_a, which is still the old value during this process.

3. Final Answer:

   The previous value of signal_a -> Option A

4. Quick Check:

   Signal update delayed, so signal_b gets old signal_a [OK]

Hint: Signal updates happen after process, so use old values inside process [OK]

Common Mistakes:

• Assuming signal_a updates immediately
• Confusing signals with variables
• Expecting signal_b to get new signal_a value instantly

4. Identify the error in the following VHDL code snippet:

process(clk)
begin
  if rising_edge(clk) then
    signal_x = '0';
  end if;
end process;

medium

A. Signal signal_x is not declared.

B. Missing semicolon after rising_edge(clk).

C. Process sensitivity list is incorrect.

D. Using = instead of <= for signal assignment.

Solution

1. Step 1: Check assignment operator used

   The code uses = to assign a value to a signal, which is incorrect in VHDL.

2. Step 2: Correct operator for signals

   Signal assignments must use <= operator.

3. Final Answer:

   Using = instead of <= for signal assignment. -> Option D

4. Quick Check:

   Signal assignment requires <= [OK]

Hint: Signals use <=, variables use := [OK]

Common Mistakes:

• Using = instead of <= for signals
• Confusing process sensitivity list
• Assuming missing semicolon causes error

5. You want to create a VHDL process that toggles a signal toggle_sig every clock cycle. Which of the following code snippets correctly uses the signal assignment operator to achieve this?

hard

A. process(clk)
begin
if rising_edge(clk) then
toggle_sig = not toggle_sig;
end if;
end process;

B. process(clk)
begin
if rising_edge(clk) then
toggle_sig <= not toggle_sig;
end if;
end process;

C. process(clk)
begin
if rising_edge(clk) then
toggle_sig := not toggle_sig;
end if;
end process;

D. process(clk)
begin
if rising_edge(clk) then
toggle_sig <= toggle_sig;
end if;
end process;

Solution

1. Step 1: Identify correct signal assignment operator

   In VHDL, signals use <= for assignment, not = or :=.

2. Step 2: Check logic for toggling signal

   Using toggle_sig <= not toggle_sig; correctly flips the signal each clock cycle.

3. Step 3: Eliminate incorrect options

   Using = or := is incorrect for signals. Assigning toggle_sig <= toggle_sig; keeps the same value, no toggle.

4. Final Answer:

   process(clk) begin if rising_edge(clk) then toggle_sig <= not toggle_sig; end if; end process; -> Option B

5. Quick Check:

   Use <= and invert signal to toggle [OK]

Hint: Toggle with <= and not operator inside clocked process [OK]

Common Mistakes:

• Using = or := instead of <= for signals
• Assigning signal to itself without change
• Forgetting to use rising_edge(clk)