Signal assignment operator in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output of this VHDL process with signal assignment?

Consider the following VHDL process. What will be the value of signal_out after the process executes once?

VHDL

signal signal_out : std_logic := '0';
begin
  process
  begin
    signal_out <= '1';
    wait for 10 ns;
  end process;

A signal_out = '0' immediately after process starts

B signal_out = '1' immediately after process starts

C signal_out = '1' after 10 ns delay

D signal_out remains '0' forever

💡 Hint

Remember that signal assignments in VHDL take effect after the process suspends.

Signal assignments in VHDL do not update the signal immediately. The new value is scheduled and takes effect after the process suspends or after delta cycles. Here, signal_out will change to '1' upon process suspension (in the next delta cycle).

❓ Predict Output

intermediate

What is the output of multiple signal assignments in one process?

Given this VHDL process, what will be the final value of sig after the process runs?

VHDL

signal sig : std_logic := '0';
begin
  process
  begin
    sig <= '1';
    sig <= '0';
    wait for 5 ns;
  end process;

A sig = '1' immediately

B sig = '1' after 5 ns

C sig = '0' after 5 ns

D sig = '0' immediately

💡 Hint

Later signal assignments override earlier ones within the same process execution.

Within a single process execution, the last signal assignment determines the final value. Here, sig is assigned '1' then '0', so it will be '0' after the process suspends (after 5 ns).

🔧 Debug

advanced

Identify the error in this signal assignment code

What error will this VHDL code produce?

VHDL

signal a : std_logic := '0';
begin
  process
  begin
    a = '1';
    wait for 10 ns;
  end process;

A Syntax error: missing semicolon after assignment

B Runtime error: signal 'a' not initialized

C No error, code runs fine

D Syntax error: '=' used instead of '<=' for signal assignment

💡 Hint

Check the correct operator for signal assignment in VHDL.

In VHDL, signals are assigned using the '<=' operator, not '=' which is used for variables or comparisons.

🧠 Conceptual

advanced

How does signal assignment timing affect simulation?

Which statement best describes when a signal assignment takes effect in VHDL?

A Signal assignments take effect after the process suspends and delta cycles complete

B Signal assignments take effect immediately when executed in the process

C Signal assignments take effect only after the entire simulation cycle ends

D Signal assignments take effect only if the signal is a variable

💡 Hint

Think about how VHDL schedules signal updates.

Signal assignments in VHDL are scheduled and take effect after the process suspends and all delta cycles are processed, not immediately.

🚀 Application

expert

Determine the final signal value after multiple processes assign it

Given two concurrent processes assigning to the same signal sig, what is the final value of sig after 20 ns?

VHDL

signal sig : std_logic := '0';

process_1: process
begin
  wait for 10 ns;
  sig <= '1';
  wait;
end process;

process_2: process
begin
  wait for 15 ns;
  sig <= '0';
  wait;
end process;

A sig = 'X' (driver conflict) after 20 ns

B sig = '1' after 20 ns

C sig = '0' after 20 ns

D sig = 'Z' (high impedance) after 20 ns

💡 Hint

Consider the order of signal assignments, their timing, and std_logic resolution with multiple drivers.

At 10 ns, process_1 assigns '1' (second driver undriven, equivalent to 'Z'; resolved to '1'). At 15 ns, process_2 assigns '0' (drivers now '1' and '0'; std_logic resolves to 'X'). After 20 ns, remains 'X'.