Priority encoder in VHDL - Mini Project: Build & Apply

Priority Encoder in VHDL

📖 Scenario: You are designing a simple digital circuit that takes multiple input signals and outputs the binary code of the highest priority active input.This is useful in devices like keyboards or interrupt controllers where multiple signals may arrive, but only the highest priority one should be processed.

🎯 Goal: Build a priority encoder in VHDL that takes a 4-bit input and outputs a 2-bit binary code representing the highest priority input bit that is set to '1'.

📋 What You'll Learn

Create a 4-bit input signal called input_signals.

Create a 2-bit output signal called output_code.

Create a 1-bit output signal called valid to indicate if any input is active.

Implement priority encoding logic where input bit 3 has the highest priority and bit 0 the lowest.

Output the binary code of the highest priority active input on output_code.

Set valid to '1' if any input bit is '1', otherwise '0'.

💡 Why This Matters

🌍 Real World

Priority encoders are used in hardware devices to select the highest priority signal among many, such as in interrupt controllers or keyboard input processing.

💼 Career

Understanding priority encoders is important for hardware engineers and FPGA designers working on digital logic circuits and embedded systems.

1

Create the input and output signals

Write the VHDL entity declaration named priority_encoder with a 4-bit input port called input_signals and two output ports: a 2-bit output_code and a 1-bit valid.

VHDL

entity priority_encoder is
    Port (
        input_signals : in std_logic_vector(3 downto 0);
        output_code : out std_logic_vector(1 downto 0);
        valid : out std_logic
    );
end priority_encoder;

architecture Behavioral of priority_encoder is
begin
    -- Your code here
end Behavioral;

Need a hint?

Define the entity with the exact port names and types as specified.

2

Add a signal to hold the encoded output

Inside the Behavioral architecture, declare a signal called encoded_output of type std_logic_vector(1 downto 0) to hold the intermediate binary code.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity priority_encoder is
    Port (
        input_signals : in std_logic_vector(3 downto 0);
        output_code : out std_logic_vector(1 downto 0);
        valid : out std_logic
    );
end priority_encoder;

architecture Behavioral of priority_encoder is
    signal encoded_output : std_logic_vector(1 downto 0);
begin
    -- Your code here
end Behavioral;

Need a hint?

Declare the signal inside the architecture but before the begin keyword.

3

Implement the priority encoding logic

Inside the architecture's begin-end block, write a process that uses input_signals to set encoded_output to the binary code of the highest priority bit set to '1'. Also set valid to '1' if any input bit is '1', else '0'. Use if-elsif statements checking bits from 3 down to 0.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity priority_encoder is
    Port (
        input_signals : in std_logic_vector(3 downto 0);
        output_code : out std_logic_vector(1 downto 0);
        valid : out std_logic
    );
end priority_encoder;

architecture Behavioral of priority_encoder is
    signal encoded_output : std_logic_vector(1 downto 0);
begin
    process(input_signals)
    begin
        if input_signals(3) = '1' then
            encoded_output <= "11";
            valid <= '1';
        elsif input_signals(2) = '1' then
            encoded_output <= "10";
            valid <= '1';
        elsif input_signals(1) = '1' then
            encoded_output <= "01";
            valid <= '1';
        elsif input_signals(0) = '1' then
            encoded_output <= "00";
            valid <= '1';
        else
            encoded_output <= "00";
            valid <= '0';
        end if;
    end process
end Behavioral;

Need a hint?

Use a process triggered by input_signals and check bits from highest to lowest priority.

4

Test the priority encoder output

Write a simple testbench process inside the architecture that sets input_signals to "0101" and then prints the values of output_code and valid using report statements.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity priority_encoder is
    Port (
        input_signals : in std_logic_vector(3 downto 0);
        output_code : out std_logic_vector(1 downto 0);
        valid : out std_logic
    );
end priority_encoder;

architecture Behavioral of priority_encoder is
    signal encoded_output : std_logic_vector(1 downto 0);
    signal test_input : std_logic_vector(3 downto 0) := (others => '0');
begin
    process(input_signals)
    begin
        if input_signals(3) = '1' then
            encoded_output <= "11";
            valid <= '1';
        elsif input_signals(2) = '1' then
            encoded_output <= "10";
            valid <= '1';
        elsif input_signals(1) = '1' then
            encoded_output <= "01";
            valid <= '1';
        elsif input_signals(0) = '1' then
            encoded_output <= "00";
            valid <= '1';
        else
            encoded_output <= "00";
            valid <= '0';
        end if;
    end process;

    output_code <= encoded_output;

    -- Your code here
end Behavioral;

Need a hint?

Use a process without sensitivity list to assign test input and use report statements to print output_code and valid.