Priority encoder in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of a 4-to-2 Priority Encoder

What is the output of this 4-to-2 priority encoder when the input is "1010"?

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity priority_encoder is
    Port ( input : in STD_LOGIC_VECTOR (3 downto 0);
           output : out STD_LOGIC_VECTOR (1 downto 0);
           valid : out STD_LOGIC);
end priority_encoder;

architecture Behavioral of priority_encoder is
begin
    process(input)
    begin
        valid <= '0';
        output <= "00";
        if input(3) = '1' then
            output <= "11";
            valid <= '1';
        elsif input(2) = '1' then
            output <= "10";
            valid <= '1';
        elsif input(1) = '1' then
            output <= "01";
            valid <= '1';
        elsif input(0) = '1' then
            output <= "00";
            valid <= '1';
        end if;
    end process;
end Behavioral;

A output = "11", valid = '1'

B output = "10", valid = '1'

C output = "01", valid = '1'

D output = "00", valid = '1'

💡 Hint

Remember the priority encoder outputs the highest priority bit set to 1.

The input "1010" means bits 3 and 1 are set. The highest priority bit is bit 3, so output is "11" and valid is '1'.

🧠 Conceptual

intermediate

Understanding Priority Encoder Valid Signal

In a priority encoder, what does the 'valid' output signal indicate?

A It resets the encoder output.

B It shows the highest priority input bit index.

C It indicates if any input bit is set to 1.

D It enables the input signals.

💡 Hint

Think about when the encoder should output a valid code.

The 'valid' signal is '1' only when at least one input bit is set to 1, indicating the output code is meaningful.

🔧 Debug

advanced

Identify the Error in Priority Encoder Code

What error will this VHDL priority encoder code produce when compiled?

VHDL

architecture Behavioral of priority_encoder is
begin
    process(input)
    begin
        valid <= '0';
        output <= "00";
        if input(3) = '1' then
            output <= "11";
            valid <= '1';
        elsif input(2) = '1' then
            output <= "10";
            valid <= '1';
        elsif input(1) = '1' then
            output <= "01";
            valid <= '1';
        elsif input(0) = '1' then
            output <= "00";
            valid <= '1';
        end if;
    end process;
end Behavioral;

A TypeError: Mismatched signal types

B RuntimeError: Signal assignment conflict

C No error, code compiles successfully

D SyntaxError: Missing semicolon after 'end if'

💡 Hint

Check the syntax of the if statement endings.

The 'end if' statement is missing a semicolon, which is required in VHDL syntax.

📝 Syntax

advanced

Correct VHDL Signal Declaration for Priority Encoder Output

Which of the following is the correct way to declare the output signal for a 3-bit priority encoder output in VHDL?

A output : out STD_LOGIC_VECTOR(0 to 2);

B output : out STD_LOGIC_VECTOR(2 downto 0);

C output : out STD_LOGIC_VECTOR(3 downto 0);

D output : in STD_LOGIC_VECTOR(3 downto 1);

💡 Hint

Remember the output should be 3 bits wide and an output port.

Option B correctly declares a 3-bit output vector from bit 2 down to 0.

🚀 Application

expert

Priority Encoder Output for Multiple Inputs Set

Given a 5-bit input to a priority encoder with bit 4 as highest priority and bit 0 as lowest, what is the output when input = "01101"?

A Output = "011", valid = '1'

B Output = "010", valid = '1'

C Output = "100", valid = '1'

D Output = "101", valid = '1'

💡 Hint

Find the highest priority bit set to 1 and output its index in binary.

Input "01101" means bits 3, 2, and 0 are set. Highest priority set bit is bit 3, which is binary "011".