Port modes (in, out, inout, buffer) in VHDL - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare an input port named clk.

VHDL

entity example is
  port (
    clk : [1] std_logic
  );
end example;

Drag options to blanks, or click blank then click option'

Ainout

Bin

Cbuffer

Dout

Attempts:

3 left

💡 Hint

Common Mistakes

Using out instead of in for input ports.

Confusing buffer with in.

The in mode is used for input ports in VHDL.

2fill in blank

medium

Complete the code to declare an output port named data_out.

VHDL

entity example is
  port (
    data_out : [1] std_logic_vector(7 downto 0)
  );
end example;

Drag options to blanks, or click blank then click option'

Aout

Bin

Cinout

Dbuffer

Attempts:

3 left

💡 Hint

Common Mistakes

Using in instead of out for output ports.

Using buffer unnecessarily.

The out mode is used for output ports in VHDL.

3fill in blank

hard

Fix the error in the port declaration to allow bidirectional data on data_bus.

VHDL

entity example is
  port (
    data_bus : [1] std_logic_vector(15 downto 0)
  );
end example;

Drag options to blanks, or click blank then click option'

Abuffer

Bout

Cin

Dinout

Attempts:

3 left

💡 Hint

Common Mistakes

Using out or in for bidirectional ports.

Confusing buffer with inout.

The inout mode allows signals to flow both in and out, enabling bidirectional ports.

4fill in blank

hard

Fill both blanks to declare a port status that can be read inside the entity and driven as output.

VHDL

entity example is
  port (
    status : [1] std_logic;
    signal_out : [2] std_logic
  );
end example;

Drag options to blanks, or click blank then click option'

Abuffer

Bin

Cout

Dinout

Attempts:

3 left

💡 Hint

Common Mistakes

Using in for ports that need to drive signals.

Using inout when buffer is more appropriate.

The buffer mode allows the signal to be read inside the entity and driven as output. The out mode is for output-only ports.

5fill in blank

hard

Fill all three blanks to declare ports: clk as input, data as bidirectional, and ready as output.

VHDL

entity example is
  port (
    clk : [1] std_logic;
    data : [2] std_logic_vector(7 downto 0);
    ready : [3] std_logic
  );
end example;

Drag options to blanks, or click blank then click option'

Ainout

Bin

Cout

Dbuffer

Attempts:

3 left

💡 Hint

Common Mistakes

Mixing up inout and buffer modes.

Using buffer for input ports.

clk is an input port, so use in. data is bidirectional, so use inout. ready is output, so use out.