Port modes (in, out, inout, buffer) in VHDL - Mini Project: Build & Apply

Understanding Port Modes in VHDL

📖 Scenario: You are designing a simple digital circuit in VHDL that uses different port modes to control data flow. Understanding how in, out, inout, and buffer ports work is essential for correct hardware behavior.

🎯 Goal: Build a VHDL entity and architecture that demonstrates the use of all four port modes: in, out, inout, and buffer. You will create signals and assign values to see how data flows through these ports.

📋 What You'll Learn

Create an entity named PortModesDemo with ports using all four modes.

Declare internal signals to connect ports where needed.

Write an architecture that assigns values to the ports and signals.

Simulate or print the output to observe port behavior.

💡 Why This Matters

🌍 Real World

Port modes in VHDL are used to define how signals flow between components in digital hardware designs, such as FPGAs and ASICs.

💼 Career

Understanding port modes is essential for hardware engineers and FPGA developers to correctly design and debug digital circuits.

1

Create the VHDL entity with all port modes

Write an entity named PortModesDemo with four ports: input_signal as in std_logic, output_signal as out std_logic, inout_signal as inout std_logic, and buffer_signal as buffer std_logic.

VHDL

-- Your code here
-- Define entity PortModesDemo with ports input_signal, output_signal, inout_signal, buffer_signal

Need a hint?

Remember to list all ports inside the port(...) block with their exact names and modes.

2

Add architecture and internal signals

Add an architecture named Behavior for PortModesDemo. Inside it, declare two internal signals: internal_inout and internal_buffer, both of type std_logic.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity PortModesDemo is
    port(
        input_signal  : in std_logic;
        output_signal : out std_logic;
        inout_signal  : inout std_logic;
        buffer_signal : buffer std_logic
    );
end PortModesDemo;

architecture Behavior of PortModesDemo is
    -- Declare internal signals here
    -- Your code here

Need a hint?

Signals are declared inside the architecture before the begin keyword.

3

Assign signals and ports inside architecture

Inside the Behavior architecture, write concurrent signal assignments: assign output_signal to input_signal, assign internal_inout to inout_signal, assign inout_signal to internal_inout, and assign buffer_signal to internal_buffer. Also assign internal_buffer to buffer_signal.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity PortModesDemo is
    port(
        input_signal  : in std_logic;
        output_signal : out std_logic;
        inout_signal  : inout std_logic;
        buffer_signal : buffer std_logic
    );
end PortModesDemo;

architecture Behavior of PortModesDemo is
    signal internal_inout  : std_logic;
    signal internal_buffer : std_logic;
begin
    -- Add signal assignments here
    -- Your code here

Need a hint?

Use concurrent signal assignment with the <= operator to connect ports and signals.

4

Simulate and observe port behavior

Write a simple testbench process inside the Behavior architecture that sets input_signal to '1', inout_signal to 'Z' (high impedance), and buffer_signal to '0'. Then print the values of output_signal, inout_signal, and buffer_signal using report statements.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity PortModesDemo is
    port(
        input_signal  : in std_logic;
        output_signal : out std_logic;
        inout_signal  : inout std_logic;
        buffer_signal : buffer std_logic
    );
end PortModesDemo;

architecture Behavior of PortModesDemo is
    signal internal_inout  : std_logic;
    signal internal_buffer : std_logic;
begin
    output_signal <= input_signal;
    internal_inout <= inout_signal;
    inout_signal <= internal_inout;
    buffer_signal <= internal_buffer;
    internal_buffer <= buffer_signal;

    process
    begin
        -- Set input_signal to '1'
        -- Set inout_signal to 'Z'
        -- Set buffer_signal to '0'
        -- Print output_signal, inout_signal, buffer_signal
        -- Your code here
        wait;
    end process;

Need a hint?

Use a process to assign values and report statements to print signal values. Use wait for 10 ns; to allow signal propagation.