Concatenation operator (&) in VHDL - Step-by-Step Execution

Concept Flow - Concatenation operator (&)

Start with signals A and B

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Apply & operator: A & B

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Create new signal with bits of A followed by bits of B

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Use concatenated signal in design

The & operator joins two bit vectors or signals by placing bits of the first signal before bits of the second, creating a longer combined signal.

Execution Sample

VHDL

signal A : std_logic_vector(3 downto 0) := "1010";
signal B : std_logic_vector(3 downto 0) := "1100";
signal C : std_logic_vector(7 downto 0);

C <= A & B;

This code concatenates two 4-bit signals A and B into an 8-bit signal C.

Execution Table

Step	Action	Signal A	Signal B	Concatenation (A & B)	Signal C Assigned
1	Initialize A	1010	-	-	-
2	Initialize B	-	1100	-	-
3	Concatenate A & B	1010	1100	10101100	-
4	Assign concatenation to C	1010	1100	10101100	10101100
5	End	1010	1100	10101100	10101100

💡 Concatenation completed and assigned to signal C

Variable Tracker

Variable	Start	After Concatenation	Final
A	1010	1010	1010
B	1100	1100	1100
C	undefined	10101100	10101100

Key Moments - 2 Insights

Why does the concatenated signal C have 8 bits instead of 4?

Because the & operator joins all bits of A (4 bits) followed by all bits of B (4 bits), making a total of 8 bits as shown in execution_table row 3.

Can we concatenate signals of different lengths?

Yes, the & operator can join signals of different lengths, resulting in a combined signal whose length is the sum of both, similar to how A and B are joined here.

Visual Quiz - 3 Questions

Look at the execution_table at step 3, what is the value of the concatenation A & B?

A 1010

B 11001010

C 10101100

D 1100

💡 Hint

Check the 'Concatenation (A & B)' column at step 3 in the execution_table.

At which step is the concatenated value assigned to signal C?

A Step 4

B Step 3

C Step 2

D Step 5

💡 Hint

Look at the 'Signal C Assigned' column in the execution_table.

If signal B was "0011" instead of "1100", what would be the concatenated result at step 3?

A 11001010

B 10100011

C 00111010

D 10101100

💡 Hint

Concatenation joins A bits then B bits, so replace B's bits in the concatenation column.

Concept Snapshot

Concatenation operator (&) in VHDL joins two signals by placing bits of the first signal before the second.
Syntax: result <= signal1 & signal2;
Result length = length(signal1) + length(signal2).
Used to combine bit vectors into longer vectors.
Example: "1010" & "1100" = "10101100".

Full Transcript

In VHDL, the concatenation operator & combines two signals by placing the bits of the first signal before the bits of the second. For example, if signal A is "1010" and signal B is "1100", then A & B results in "10101100". This combined signal can be assigned to another signal, like C. The length of the new signal is the sum of the lengths of the two original signals. This operation is useful to build wider signals from smaller parts.