Concatenation operator (&) in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output of this VHDL signal assignment?

Consider the following VHDL code snippet:

signal A : std_logic_vector(3 downto 0) := "1010";
signal B : std_logic_vector(3 downto 0) := "1100";
signal C : std_logic_vector(7 downto 0);

C <= A & B;

What is the value of signal C after this assignment?

VHDL

signal A : std_logic_vector(3 downto 0) := "1010";
signal B : std_logic_vector(3 downto 0) := "1100";
signal C : std_logic_vector(7 downto 0);

C <= A & B;

A "11001010"

B "10101100"

C "1010 1100"

D "11110000"

💡 Hint

Remember that the & operator joins two vectors by placing the left operand bits first, then the right operand bits.

The concatenation operator (&) joins the bits of A and B in order. Since A is "1010" and B is "1100", C becomes "10101100".

❓ Predict Output

intermediate

What is the length of the resulting vector?

Given the following VHDL code:

signal X : std_logic_vector(7 downto 0);
signal Y : std_logic_vector(3 downto 0);
signal Z : std_logic_vector(11 downto 0);

Z <= X & Y;

What is the length of signal Z after the concatenation?

VHDL

signal X : std_logic_vector(7 downto 0);
signal Y : std_logic_vector(3 downto 0);
signal Z : std_logic_vector(11 downto 0);

Z <= X & Y;

A 12 bits

B 11 bits

C 8 bits

D 4 bits

💡 Hint

Add the lengths of both vectors being concatenated.

X has 8 bits (7 downto 0) and Y has 4 bits (3 downto 0). Concatenating them results in 8 + 4 = 12 bits.

🔧 Debug

advanced

Why does this concatenation cause a compilation error?

Examine the following VHDL code:

signal A : std_logic_vector(3 downto 0);
signal B : std_logic_vector(2 downto 0);
signal C : std_logic_vector(7 downto 0);

C <= A & B;

Why does this code cause a compilation error?

VHDL

signal A : std_logic_vector(3 downto 0);
signal B : std_logic_vector(2 downto 0);
signal C : std_logic_vector(7 downto 0);

C <= A & B;

A Because the length of A & B is 7 bits, which does not match C's 8 bits

B Because concatenation (&) cannot be used with std_logic_vector

C Because signal C is not initialized

D Because signals A and B have different directions (downto)

💡 Hint

Check the total length of the concatenated vector and compare it to C's length.

A has 4 bits, B has 3 bits, so A & B has 7 bits total. But C is declared as 7 downto 0, which is 8 bits. The sizes don't match, causing an error.

📝 Syntax

advanced

Which option correctly concatenates two std_logic_vectors?

Select the correct VHDL syntax to concatenate two std_logic_vectors A and B into C:

VHDL

signal A, B : std_logic_vector(3 downto 0);
signal C : std_logic_vector(7 downto 0);

A C <= A . B;

B C <= A + B;

C C <= A & B;

D C <= concat(A, B);

💡 Hint

The concatenation operator in VHDL is &.

Only option C uses the correct concatenation operator (&). Options A, B, and C are invalid syntax or functions.

🚀 Application

expert

What is the output of this concatenation and slicing operation?

Given the following VHDL code:

signal A : std_logic_vector(7 downto 0) := "10110011";
signal B : std_logic_vector(3 downto 0) := "1101";
signal C : std_logic_vector(7 downto 0);

C <= (A & B)(11 downto 4);

What is the value of signal C after this assignment?

VHDL

signal A : std_logic_vector(7 downto 0) := "10110011";
signal B : std_logic_vector(3 downto 0) := "1101";
signal C : std_logic_vector(7 downto 0);

C <= (A & B)(11 downto 4);

A "10111101"

B "11001101"

C "11011100"

D "10110011"

💡 Hint

Concatenate A and B, then select bits 11 downto 4 from the result.

Concatenation A & B is 12 bits: bits 11 downto 0 = A(7 downto 0) & B(3 downto 0) = "101100111101". Selecting bits 11 downto 4 gives the upper 8 bits "10110011", which is assigned to C.