Concatenation operator (&) in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output of this VHDL signal assignment?

Consider the following VHDL code snippet:

signal A : std_logic_vector(3 downto 0) := "1010";
signal B : std_logic_vector(3 downto 0) := "1100";
signal C : std_logic_vector(7 downto 0);

C <= A & B;

What is the value of signal C after this assignment?

VHDL

signal A : std_logic_vector(3 downto 0) := "1010";
signal B : std_logic_vector(3 downto 0) := "1100";
signal C : std_logic_vector(7 downto 0);

C <= A & B;

A "11001010"

B "10101100"

C "1010 1100"

D "11110000"

💡 Hint

Remember that the & operator joins two vectors by placing the left operand bits first, then the right operand bits.

The concatenation operator (&) joins the bits of A and B in order. Since A is "1010" and B is "1100", C becomes "10101100".

❓ Predict Output

intermediate

What is the length of the resulting vector?

Given the following VHDL code:

signal X : std_logic_vector(7 downto 0);
signal Y : std_logic_vector(3 downto 0);
signal Z : std_logic_vector(11 downto 0);

Z <= X & Y;

What is the length of signal Z after the concatenation?

VHDL

signal X : std_logic_vector(7 downto 0);
signal Y : std_logic_vector(3 downto 0);
signal Z : std_logic_vector(11 downto 0);

Z <= X & Y;

A 12 bits

B 11 bits

C 8 bits

D 4 bits

💡 Hint

Add the lengths of both vectors being concatenated.

X has 8 bits (7 downto 0) and Y has 4 bits (3 downto 0). Concatenating them results in 8 + 4 = 12 bits.

🔧 Debug

advanced

Why does this concatenation cause a compilation error?

Examine the following VHDL code:

signal A : std_logic_vector(3 downto 0);
signal B : std_logic_vector(2 downto 0);
signal C : std_logic_vector(7 downto 0);

C <= A & B;

Why does this code cause a compilation error?

VHDL

signal A : std_logic_vector(3 downto 0);
signal B : std_logic_vector(2 downto 0);
signal C : std_logic_vector(7 downto 0);

C <= A & B;

A Because the length of A & B is 7 bits, which does not match C's 8 bits

B Because concatenation (&) cannot be used with std_logic_vector

C Because signal C is not initialized

D Because signals A and B have different directions (downto)

💡 Hint

Check the total length of the concatenated vector and compare it to C's length.

A has 4 bits, B has 3 bits, so A & B has 7 bits total. But C is declared as 7 downto 0, which is 8 bits. The sizes don't match, causing an error.

📝 Syntax

advanced

Which option correctly concatenates two std_logic_vectors?

Select the correct VHDL syntax to concatenate two std_logic_vectors A and B into C:

VHDL

signal A, B : std_logic_vector(3 downto 0);
signal C : std_logic_vector(7 downto 0);

A C <= A . B;

B C <= A + B;

C C <= A & B;

D C <= concat(A, B);

💡 Hint

The concatenation operator in VHDL is &.

Only option C uses the correct concatenation operator (&). Options A, B, and C are invalid syntax or functions.

🚀 Application

expert

What is the output of this concatenation and slicing operation?

Given the following VHDL code:

signal A : std_logic_vector(7 downto 0) := "10110011";
signal B : std_logic_vector(3 downto 0) := "1101";
signal C : std_logic_vector(7 downto 0);

C <= (A & B)(11 downto 4);

What is the value of signal C after this assignment?

VHDL

signal A : std_logic_vector(7 downto 0) := "10110011";
signal B : std_logic_vector(3 downto 0) := "1101";
signal C : std_logic_vector(7 downto 0);

C <= (A & B)(11 downto 4);

A "10111101"

B "11001101"

C "11011100"

D "10110011"

💡 Hint

Concatenate A and B, then select bits 11 downto 4 from the result.

Concatenation A & B is 12 bits: bits 11 downto 0 = A(7 downto 0) & B(3 downto 0) = "101100111101". Selecting bits 11 downto 4 gives the upper 8 bits "10110011", which is assigned to C.

Practice

1. What does the VHDL concatenation operator & do?

easy

A. Joins two or more bit vectors or bits into one longer vector

B. Performs bitwise AND operation between two vectors

C. Splits a vector into smaller parts

D. Assigns a value to a signal

Solution

1. Step 1: Understand the operator's purpose

   The & operator in VHDL is used to join bits or bit vectors together.

2. Step 2: Differentiate from other operators

   Unlike bitwise AND, it concatenates bits side by side to form a longer vector.

3. Final Answer:

   Joins two or more bit vectors or bits into one longer vector -> Option A

4. Quick Check:

   Concatenation = Joining bits [OK]

Hint: Remember & joins bits side by side, not bitwise AND [OK]

Common Mistakes:

• Confusing & with bitwise AND
• Thinking & splits vectors
• Assuming & assigns values

2. Which of the following is the correct syntax to concatenate two std_logic_vectors A and B in VHDL?

easy

A. C <= A & B;

B. C <= A + B;

C. C <= A and B;

D. C <= A | B;

Solution

1. Step 1: Identify concatenation syntax

   In VHDL, concatenation uses the & operator between vectors.

2. Step 2: Check other operators

   + is arithmetic addition, and is bitwise AND, | is not valid in VHDL for concatenation.

3. Final Answer:

   C <= A & B; -> Option A

4. Quick Check:

   Concatenation uses & operator [OK]

Hint: Use & to join vectors, not + or and [OK]

Common Mistakes:

• Using + instead of & for concatenation
• Using bitwise operators like and
• Using | which is invalid in VHDL

3. Given the following VHDL code:

signal A : std_logic_vector(3 downto 0) := "1010";
signal B : std_logic_vector(1 downto 0) := "11";
signal C : std_logic_vector(5 downto 0);

C <= A & B;

What is the value of C after the assignment?

medium

A. "1010"

B. "101011"

C. "111010"

D. "1111"

Solution

1. Step 1: Understand concatenation order

   The operator & joins A first, then B, so bits of A come first.

2. Step 2: Combine the bit vectors

   A is "1010" and B is "11", so concatenation is "1010" & "11" = "101011".

3. Final Answer:

   "101011" -> Option B

4. Quick Check:

   Concatenate A then B = 101011 [OK]

Hint: Left side bits come first in concatenation [OK]

Common Mistakes:

• Reversing order of concatenation
• Confusing concatenation with addition
• Ignoring vector sizes

4. Consider this VHDL snippet:

signal X : std_logic_vector(3 downto 0) := "1100";
signal Y : std_logic_vector(3 downto 0);

Y <= X & '1';

What is the error in this code?

medium

A. Single quotes used incorrectly for bit literal

B. Cannot concatenate a vector and a single bit directly

C. Signal Y has wrong size for concatenation result

D. No error, code is correct

Solution

1. Step 1: Check sizes of signals

   X is 4 bits, concatenated with one bit '1' makes 5 bits total.

2. Step 2: Compare with target signal size

   Y is declared as 4 bits, which cannot hold 5 bits from concatenation.

3. Final Answer:

   Signal Y has wrong size for concatenation result -> Option C

4. Quick Check:

   Concatenation size must match target signal size [OK]

Hint: Check target signal size matches concatenation length [OK]

Common Mistakes:

• Assuming single bit can't concatenate with vector
• Ignoring size mismatch errors
• Thinking single quotes are wrong for bits

5. You want to create an 8-bit vector DATA by concatenating a 3-bit vector A, a 2-bit vector B, and a 3-bit vector C. Which of the following assignments is correct in VHDL?

hard

A. DATA <= (A & B) or C;

B. DATA <= B & A & C;

C. DATA <= A and (B & C);

D. DATA <= A & B & C;

Solution

1. Step 1: Determine the correct concatenation

   To join A (3 bits), B (2 bits), C (3 bits) into 8-bit DATA, use DATA <= A & B & C; which appends them in order.

2. Step 2: Eliminate incorrect options

   B reverses order to B A C, C mixes 'and' operator, D uses 'or' after partial concat.

3. Final Answer:

   DATA <= A & B & C; -> Option D

4. Quick Check:

   3+2+3=8 bits, A&B&C [OK]

Hint: Always concatenate in the specified order using & [OK]

Common Mistakes:

• Reversing the concatenation order
• Mixing bitwise operators (and, or) with concatenation (&)
• Assuming different operator precedence changes order