Concatenation operator (&) in VHDL - Mini Project: Build & Apply

Using the Concatenation Operator (&) in VHDL

📖 Scenario: You are designing a simple digital system in VHDL that combines two 4-bit signals into one 8-bit signal. This is a common task when you want to join smaller data parts into a bigger bus.

🎯 Goal: Build a VHDL code snippet that uses the concatenation operator & to join two 4-bit vectors into one 8-bit vector.

📋 What You'll Learn

Create two 4-bit std_logic_vector signals with exact values

Create an 8-bit std_logic_vector signal to hold the concatenated result

Use the concatenation operator & to join the two 4-bit signals

Print the concatenated 8-bit vector in a testbench process

💡 Why This Matters

🌍 Real World

Concatenation is used in hardware design to combine smaller buses into larger ones, like joining address and data lines.

💼 Career

Understanding concatenation helps in FPGA and ASIC design jobs where signal manipulation is common.

1

DATA SETUP: Declare two 4-bit signals

Declare two signals called part1 and part2 of type std_logic_vector(3 downto 0). Set part1 to "1010" and part2 to "1100".

VHDL

-- Declare signals part1 and part2 here
-- Your code here

Need a hint?

Use signal keyword to declare signals and assign the exact bit strings.

2

CONFIGURATION: Declare an 8-bit signal for the result

Declare a signal called combined of type std_logic_vector(7 downto 0) to hold the concatenated result.

VHDL

signal part1 : std_logic_vector(3 downto 0) := "1010";
signal part2 : std_logic_vector(3 downto 0) := "1100";
-- Declare signal combined here
-- Your code here

Need a hint?

Remember to declare combined as an 8-bit vector without initial value.

3

CORE LOGIC: Use the concatenation operator & to join signals

Assign combined the value of part1 & part2 using the concatenation operator & inside a process or concurrent assignment.

VHDL

signal part1 : std_logic_vector(3 downto 0) := "1010";
signal part2 : std_logic_vector(3 downto 0) := "1100";
signal combined : std_logic_vector(7 downto 0);
-- Assign combined the concatenation of part1 and part2
-- Your code here

Need a hint?

Use the & operator between part1 and part2 to join them.

4

OUTPUT: Print the concatenated signal in a testbench process

Write a simple process that waits for 10 ns and then uses report to print the value of combined as a string.

VHDL

signal part1 : std_logic_vector(3 downto 0) := "1010";
signal part2 : std_logic_vector(3 downto 0) := "1100";
signal combined : std_logic_vector(7 downto 0);

combined <= part1 & part2;

-- Add a process to wait 10 ns and report combined
-- Your code here

Need a hint?

Use a process with wait for 10 ns; and report statement. Use to_string() or appropriate conversion to convert the vector to string.