Concatenation operator (&) in VHDL - Mini Project: Build & Apply

Using the Concatenation Operator (&) in VHDL

📖 Scenario: You are designing a simple digital system in VHDL that combines two 4-bit signals into one 8-bit signal. This is a common task when you want to join smaller data parts into a bigger bus.

🎯 Goal: Build a VHDL code snippet that uses the concatenation operator & to join two 4-bit vectors into one 8-bit vector.

📋 What You'll Learn

Create two 4-bit std_logic_vector signals with exact values

Create an 8-bit std_logic_vector signal to hold the concatenated result

Use the concatenation operator & to join the two 4-bit signals

Print the concatenated 8-bit vector in a testbench process

💡 Why This Matters

🌍 Real World

Concatenation is used in hardware design to combine smaller buses into larger ones, like joining address and data lines.

💼 Career

Understanding concatenation helps in FPGA and ASIC design jobs where signal manipulation is common.

1

DATA SETUP: Declare two 4-bit signals

Declare two signals called part1 and part2 of type std_logic_vector(3 downto 0). Set part1 to "1010" and part2 to "1100".

VHDL

-- Declare signals part1 and part2 here
-- Your code here

Hint

Use signal keyword to declare signals and assign the exact bit strings.

2

CONFIGURATION: Declare an 8-bit signal for the result

Declare a signal called combined of type std_logic_vector(7 downto 0) to hold the concatenated result.

VHDL

signal part1 : std_logic_vector(3 downto 0) := "1010";
signal part2 : std_logic_vector(3 downto 0) := "1100";
-- Declare signal combined here
-- Your code here

Hint

Remember to declare combined as an 8-bit vector without initial value.

3

CORE LOGIC: Use the concatenation operator & to join signals

Assign combined the value of part1 & part2 using the concatenation operator & inside a process or concurrent assignment.

VHDL

signal part1 : std_logic_vector(3 downto 0) := "1010";
signal part2 : std_logic_vector(3 downto 0) := "1100";
signal combined : std_logic_vector(7 downto 0);
-- Assign combined the concatenation of part1 and part2
-- Your code here

Hint

Use the & operator between part1 and part2 to join them.

4

OUTPUT: Print the concatenated signal in a testbench process

Write a simple process that waits for 10 ns and then uses report to print the value of combined as a string.

VHDL

signal part1 : std_logic_vector(3 downto 0) := "1010";
signal part2 : std_logic_vector(3 downto 0) := "1100";
signal combined : std_logic_vector(7 downto 0);

combined <= part1 & part2;

-- Add a process to wait 10 ns and report combined
-- Your code here

Hint

Use a process with wait for 10 ns; and report statement. Use to_string() or appropriate conversion to convert the vector to string.

Practice

1. What does the VHDL concatenation operator & do?

easy

A. Joins two or more bit vectors or bits into one longer vector

B. Performs bitwise AND operation between two vectors

C. Splits a vector into smaller parts

D. Assigns a value to a signal

Solution

1. Step 1: Understand the operator's purpose

   The & operator in VHDL is used to join bits or bit vectors together.

2. Step 2: Differentiate from other operators

   Unlike bitwise AND, it concatenates bits side by side to form a longer vector.

3. Final Answer:

   Joins two or more bit vectors or bits into one longer vector -> Option A

4. Quick Check:

   Concatenation = Joining bits [OK]

Hint: Remember & joins bits side by side, not bitwise AND [OK]

Common Mistakes:

• Confusing & with bitwise AND
• Thinking & splits vectors
• Assuming & assigns values

2. Which of the following is the correct syntax to concatenate two std_logic_vectors A and B in VHDL?

easy

A. C <= A & B;

B. C <= A + B;

C. C <= A and B;

D. C <= A | B;

Solution

1. Step 1: Identify concatenation syntax

   In VHDL, concatenation uses the & operator between vectors.

2. Step 2: Check other operators

   + is arithmetic addition, and is bitwise AND, | is not valid in VHDL for concatenation.

3. Final Answer:

   C <= A & B; -> Option A

4. Quick Check:

   Concatenation uses & operator [OK]

Hint: Use & to join vectors, not + or and [OK]

Common Mistakes:

• Using + instead of & for concatenation
• Using bitwise operators like and
• Using | which is invalid in VHDL

3. Given the following VHDL code:

signal A : std_logic_vector(3 downto 0) := "1010";
signal B : std_logic_vector(1 downto 0) := "11";
signal C : std_logic_vector(5 downto 0);

C <= A & B;

What is the value of C after the assignment?

medium

A. "1010"

B. "101011"

C. "111010"

D. "1111"

Solution

1. Step 1: Understand concatenation order

   The operator & joins A first, then B, so bits of A come first.

2. Step 2: Combine the bit vectors

   A is "1010" and B is "11", so concatenation is "1010" & "11" = "101011".

3. Final Answer:

   "101011" -> Option B

4. Quick Check:

   Concatenate A then B = 101011 [OK]

Hint: Left side bits come first in concatenation [OK]

Common Mistakes:

• Reversing order of concatenation
• Confusing concatenation with addition
• Ignoring vector sizes

4. Consider this VHDL snippet:

signal X : std_logic_vector(3 downto 0) := "1100";
signal Y : std_logic_vector(3 downto 0);

Y <= X & '1';

What is the error in this code?

medium

A. Single quotes used incorrectly for bit literal

B. Cannot concatenate a vector and a single bit directly

C. Signal Y has wrong size for concatenation result

D. No error, code is correct

Solution

1. Step 1: Check sizes of signals

   X is 4 bits, concatenated with one bit '1' makes 5 bits total.

2. Step 2: Compare with target signal size

   Y is declared as 4 bits, which cannot hold 5 bits from concatenation.

3. Final Answer:

   Signal Y has wrong size for concatenation result -> Option C

4. Quick Check:

   Concatenation size must match target signal size [OK]

Hint: Check target signal size matches concatenation length [OK]

Common Mistakes:

• Assuming single bit can't concatenate with vector
• Ignoring size mismatch errors
• Thinking single quotes are wrong for bits

5. You want to create an 8-bit vector DATA by concatenating a 3-bit vector A, a 2-bit vector B, and a 3-bit vector C. Which of the following assignments is correct in VHDL?

hard

A. DATA <= (A & B) or C;

B. DATA <= B & A & C;

C. DATA <= A and (B & C);

D. DATA <= A & B & C;

Solution

1. Step 1: Determine the correct concatenation

   To join A (3 bits), B (2 bits), C (3 bits) into 8-bit DATA, use DATA <= A & B & C; which appends them in order.

2. Step 2: Eliminate incorrect options

   B reverses order to B A C, C mixes 'and' operator, D uses 'or' after partial concat.

3. Final Answer:

   DATA <= A & B & C; -> Option D

4. Quick Check:

   3+2+3=8 bits, A&B&C [OK]

Hint: Always concatenate in the specified order using & [OK]

Common Mistakes:

• Reversing the concatenation order
• Mixing bitwise operators (and, or) with concatenation (&)
• Assuming different operator precedence changes order