Aggregate assignment in VHDL - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to assign values to the record fields using aggregate assignment.

VHDL

signal my_record : record_type;

my_record <= (field1 => [1], field2 => '0');

Drag options to blanks, or click blank then click option'

A"1100"

B'1'

C'Z'

D"1010"

Attempts:

3 left

💡 Hint

Common Mistakes

Assigning a single bit '1' to a 4-bit vector field.

Using single quotes for vectors instead of double quotes.

The field1 expects a 4-bit std_logic_vector, so "1010" is the correct aggregate value.

2fill in blank

medium

Complete the aggregate assignment to set all fields of the record.

VHDL

my_record <= (field1 => "1100", field2 => [1]);

Drag options to blanks, or click blank then click option'

A'1'

B'0'

C"1"

D"0"

Attempts:

3 left

💡 Hint

Common Mistakes

Using double quotes for single bit assignments.

Assigning a character not allowed in std_logic.

Field2 is a single std_logic bit, so it must be assigned a single character in single quotes like '0'.

3fill in blank

hard

Fix the error in the aggregate assignment to the record.

VHDL

my_record <= (field1 => [1], field2 => '1');

Drag options to blanks, or click blank then click option'

A"1010"

B"10101"

C'1010'

D'1'

Attempts:

3 left

💡 Hint

Common Mistakes

Assigning a 5-bit vector to a 4-bit field.

Using single quotes for vectors.

Field1 is a 4-bit vector, so the assigned value must be a 4-bit string in double quotes like "1010".

4fill in blank

hard

Fill both blanks to correctly assign values to the record fields using aggregate assignment.

VHDL

my_record <= (field1 => [1], field2 => [2]);

Drag options to blanks, or click blank then click option'

A"1111"

B'0'

C'1'

D"0000"

Attempts:

3 left

💡 Hint

Common Mistakes

Mixing single and double quotes incorrectly.

Assigning wrong vector length.

Field1 requires a 4-bit vector, so "1111" is correct. Field2 is a single bit, so '0' is correct.

5fill in blank

hard

Fill all three blanks to assign values to a nested record using aggregate assignment.

VHDL

my_nested_record <= (outer_field1 => [1], outer_field2 => (inner_field1 => [2], inner_field2 => [3]));

Drag options to blanks, or click blank then click option'

A"1010"

B'1'

C'0'

D"0101"

Attempts:

3 left

💡 Hint

Common Mistakes

Using wrong quotes for bits or vectors.

Not matching vector length to field size.

outer_field1 is a 4-bit vector, so "1010" is correct. inner_field1 and inner_field2 are single bits, so '1' and '0' are correct respectively.