Aggregate assignment in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of aggregate assignment with record type

What is the output value of the signal my_record after the following VHDL code executes?

VHDL

type my_type is record
  a : integer;
  b : std_logic_vector(3 downto 0);
end record;
signal my_record : my_type;

begin
  my_record <= (a => 5, b => "1010");

A (a => 10, b => "1010")

B (a => 0, b => "0000")

C (a => 5, b => "1010")

D (a => 5, b => "0101")

💡 Hint

Remember that aggregate assignment sets each field explicitly by name.

The aggregate assigns 5 to field 'a' and "1010" to field 'b'. So the signal holds those exact values.

❓ Predict Output

intermediate

Output of aggregate assignment with array type

Given the following VHDL code, what is the value of my_array after the assignment?

VHDL

type arr_type is array (0 to 3) of integer;
signal my_array : arr_type;

begin
  my_array <= (0 => 10, 1 => 20, 2 => 30, 3 => 40);

A (40, 30, 20, 10)

B (10, 20, 30, 40)

C (0, 1, 2, 3)

D (10, 20, 30, 0)

💡 Hint

Aggregate assignment uses index => value pairs for arrays.

Each index from 0 to 3 is assigned the corresponding integer value, so the array holds (10, 20, 30, 40).

❓ Predict Output

advanced

Nested aggregate assignment output

What is the value of complex_signal after this nested aggregate assignment?

VHDL

type inner_rec is record
  x : integer;
  y : std_logic;
end record;
type outer_rec is record
  a : inner_rec;
  b : std_logic_vector(1 downto 0);
end record;
signal complex_signal : outer_rec;

begin
  complex_signal <= (a => (x => 7, y => '1'), b => "01");

A (a => (x => 7, y => '1'), b => "01")

B (a => (x => 1, y => '7'), b => "10")

C (a => (x => 7, y => '0'), b => "01")

D (a => (x => 0, y => '1'), b => "11")

💡 Hint

Nested aggregates assign inner records by their own field names.

The outer record's field 'a' is assigned an inner record with x=7 and y='1', and field 'b' is assigned "01".

❓ Predict Output

advanced

Effect of partial aggregate assignment on record

Given the record type and signal below, what will be the value of rec_signal after this partial aggregate assignment?

VHDL

type rec_type is record
  p : integer := 1;
  q : integer := 2;
  r : integer := 3;
end record;
signal rec_signal : rec_type := (p => 10, q => 20, r => 30);

begin
  rec_signal <= (p => 100, q => rec_signal.q, r => rec_signal.r);

A (p => 100, q => 20, r => 30)

B (p => 100, q => 0, r => 0)

C (p => 10, q => 20, r => 30)

D (p => 100, q => 100, r => 100)

💡 Hint

Partial aggregates can reuse existing signal values for some fields.

The assignment sets p to 100, and copies q and r from the current signal values (20 and 30).

❓ Predict Output

expert

Output of aggregate assignment with unconstrained array

Consider the following VHDL code. What is the value of dyn_array after the assignment?

VHDL

type dyn_array_type is array (natural range <>) of integer;
signal dyn_array : dyn_array_type(2 to 4);

begin
  dyn_array <= (2 => 5, 3 => 10, 4 => 15);

A (0, 5, 10, 15)

B (15, 10, 5)

C (5, 10, 15, 20)

D (5, 10, 15)

💡 Hint

Unconstrained arrays can have custom index ranges; assignment uses those indices.

The signal is indexed from 2 to 4, so the values at indices 2,3,4 are 5,10,15 respectively.

Practice

1. What does an aggregate assignment in VHDL do?

easy

A. Declares a new signal or variable

B. Defines a new data type

C. Starts a process block

D. Assigns values to multiple parts of a signal or variable at once

Solution

1. Step 1: Understand aggregate assignment purpose

   Aggregate assignment allows setting several parts of a signal or variable together in one statement.

2. Step 2: Compare with other options

   Declaring signals, starting processes, or defining types are different VHDL tasks unrelated to aggregate assignment.

3. Final Answer:

   Assigns values to multiple parts of a signal or variable at once -> Option D

4. Quick Check:

   Aggregate assignment = multiple parts set together [OK]

Hint: Aggregate means setting many parts at once [OK]

Common Mistakes:

• Confusing aggregate assignment with signal declaration
• Thinking it starts a process block
• Mixing it up with type definition

2. Which of the following is the correct syntax for a named aggregate assignment in VHDL for a record r with fields a and b?

easy

A. r <= (a => '1', b => '0');

B. r <= ('1', '0');

C. r <= a = '1', b = '0';

D. r = (a: '1', b: '0');

Solution

1. Step 1: Identify named aggregate syntax

   Named aggregates use the format (field => value), separated by commas, inside parentheses.

2. Step 2: Check each option

   r <= (a => '1', b => '0'); matches named aggregate syntax. r <= ('1', '0'); is positional aggregate. Options A and C use incorrect symbols (= or :) and lack parentheses.

3. Final Answer:

   r <= (a => '1', b => '0'); -> Option A

4. Quick Check:

   Named aggregate uses => inside parentheses [OK]

Hint: Named aggregate uses => between field and value [OK]

Common Mistakes:

• Using = instead of => in named aggregates
• Omitting parentheses around aggregate
• Confusing positional and named aggregate syntax

3. Given the VHDL record type and signal:

type MyRec is record
  x : std_logic;
  y : std_logic_vector(1 downto 0);
end record;
signal r : MyRec;

What is the value of r after this assignment?

r <= (x => '1', y => "10");

medium

A. r.x = '1', r.y = "01"

B. r.x = '0', r.y = "10"

C. r.x = '1', r.y = "10"

D. r.x = '0', r.y = "00"

Solution

1. Step 1: Analyze the aggregate assignment

   The assignment sets r.x to '1' and r.y to "10" explicitly using named association.

2. Step 2: Confirm values after assignment

   Since both fields are assigned, r.x is '1' and r.y is "10" exactly as given.

3. Final Answer:

   r.x = '1', r.y = "10" -> Option C

4. Quick Check:

   Named aggregate sets fields exactly [OK]

Hint: Named aggregate sets exact field values [OK]

Common Mistakes:

• Mixing up bit order in std_logic_vector
• Assuming default values instead of assigned ones
• Confusing positional and named aggregate results

4. Identify the error in this VHDL aggregate assignment:

type T is record
  a : std_logic;
  b : std_logic_vector(1 downto 0);
end record;
signal s : T;
signal s : T;
s <= (a => '1', b => "10");

medium

A. Incorrect aggregate syntax using =>

B. Duplicate signal declaration for s

C. Missing semicolon after record type

D. Wrong vector size for b

Solution

1. Step 1: Check signal declarations

   The signal s is declared twice, which is not allowed in VHDL.

2. Step 2: Verify other syntax

   The aggregate syntax and vector size are correct, and semicolons are properly placed.

3. Final Answer:

   Duplicate signal declaration for s -> Option B

4. Quick Check:

   Two signals with same name cause error [OK]

Hint: Check for repeated signal names [OK]

Common Mistakes:

• Ignoring duplicate declarations
• Assuming => is invalid in aggregates
• Miscounting vector size

5. You have a nested record type:

type InnerRec is record
  p : std_logic;
  q : std_logic_vector(1 downto 0);
end record;
type OuterRec is record
  a : std_logic;
  b : InnerRec;
end record;
signal r : OuterRec;

Which aggregate assignment correctly sets r.a to '0', r.b.p to '1', and r.b.q to "11"?

hard

A. r <= (a => '0', b => (p => '1', q => "11"));

B. r <= (a => '0', b => p => '1', q => "11");

C. r <= (a => '0', b.p => '1', b.q => "11");

D. r <= (a => '0', b => ("11", '1'));

Solution

1. Step 1: Understand nested aggregate syntax

   For nested records, inner fields are assigned using nested aggregates inside the outer aggregate.

2. Step 2: Check each option's correctness

   r <= (a => '0', b => (p => '1', q => "11")); correctly nests the inner record assignment. r <= (a => '0', b => p => '1', q => "11"); lacks parentheses for inner aggregate. r <= (a => '0', b.p => '1', b.q => "11"); uses invalid dot notation in aggregate. r <= (a => '0', b => ("11", '1')); uses positional aggregate with incorrect element order, resulting in type mismatch.

3. Final Answer:

   r <= (a => '0', b => (p => '1', q => "11")); -> Option A

4. Quick Check:

   Nested aggregates use parentheses inside outer aggregate [OK]

Hint: Use nested parentheses for nested record fields [OK]

Common Mistakes:

• Missing parentheses for inner record aggregate
• Using dot notation inside aggregate
• Confusing positional and named aggregates in nested records