Aggregate assignment in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of aggregate assignment with record type

What is the output value of the signal my_record after the following VHDL code executes?

VHDL

type my_type is record
  a : integer;
  b : std_logic_vector(3 downto 0);
end record;
signal my_record : my_type;

begin
  my_record <= (a => 5, b => "1010");

A (a => 10, b => "1010")

B (a => 0, b => "0000")

C (a => 5, b => "1010")

D (a => 5, b => "0101")

💡 Hint

Remember that aggregate assignment sets each field explicitly by name.

The aggregate assigns 5 to field 'a' and "1010" to field 'b'. So the signal holds those exact values.

❓ Predict Output

intermediate

Output of aggregate assignment with array type

Given the following VHDL code, what is the value of my_array after the assignment?

VHDL

type arr_type is array (0 to 3) of integer;
signal my_array : arr_type;

begin
  my_array <= (0 => 10, 1 => 20, 2 => 30, 3 => 40);

A (40, 30, 20, 10)

B (10, 20, 30, 40)

C (0, 1, 2, 3)

D (10, 20, 30, 0)

💡 Hint

Aggregate assignment uses index => value pairs for arrays.

Each index from 0 to 3 is assigned the corresponding integer value, so the array holds (10, 20, 30, 40).

❓ Predict Output

advanced

Nested aggregate assignment output

What is the value of complex_signal after this nested aggregate assignment?

VHDL

type inner_rec is record
  x : integer;
  y : std_logic;
end record;
type outer_rec is record
  a : inner_rec;
  b : std_logic_vector(1 downto 0);
end record;
signal complex_signal : outer_rec;

begin
  complex_signal <= (a => (x => 7, y => '1'), b => "01");

A (a => (x => 7, y => '1'), b => "01")

B (a => (x => 1, y => '7'), b => "10")

C (a => (x => 7, y => '0'), b => "01")

D (a => (x => 0, y => '1'), b => "11")

💡 Hint

Nested aggregates assign inner records by their own field names.

The outer record's field 'a' is assigned an inner record with x=7 and y='1', and field 'b' is assigned "01".

❓ Predict Output

advanced

Effect of partial aggregate assignment on record

Given the record type and signal below, what will be the value of rec_signal after this partial aggregate assignment?

VHDL

type rec_type is record
  p : integer := 1;
  q : integer := 2;
  r : integer := 3;
end record;
signal rec_signal : rec_type := (p => 10, q => 20, r => 30);

begin
  rec_signal <= (p => 100, q => rec_signal.q, r => rec_signal.r);

A (p => 100, q => 20, r => 30)

B (p => 100, q => 0, r => 0)

C (p => 10, q => 20, r => 30)

D (p => 100, q => 100, r => 100)

💡 Hint

Partial aggregates can reuse existing signal values for some fields.

The assignment sets p to 100, and copies q and r from the current signal values (20 and 30).

❓ Predict Output

expert

Output of aggregate assignment with unconstrained array

Consider the following VHDL code. What is the value of dyn_array after the assignment?

VHDL

type dyn_array_type is array (natural range <>) of integer;
signal dyn_array : dyn_array_type(2 to 4);

begin
  dyn_array <= (2 => 5, 3 => 10, 4 => 15);

A (0, 5, 10, 15)

B (15, 10, 5)

C (5, 10, 15, 20)

D (5, 10, 15)

💡 Hint

Unconstrained arrays can have custom index ranges; assignment uses those indices.

The signal is indexed from 2 to 4, so the values at indices 2,3,4 are 5,10,15 respectively.