Mealy machine implementation in VHDL - Step-by-Step Execution

Concept Flow - Mealy machine implementation

Start

↓

Read Input

↓

Check Current State

↓

Determine Next State & Output

↓

Update State

↓

Output Signal

↓

Wait for Next Clock

↩Back to Read Input

The Mealy machine reads input and current state, then decides next state and output simultaneously, updates state, and outputs signal each clock cycle.

Execution Sample

VHDL

process(clk, reset)
begin
  if reset = '1' then
    state <= S0;
  elsif rising_edge(clk) then
    case state is
      when S0 =>
        if input = '1' then
          state <= S1;
          output <= '1';
        else
          output <= '0';
        end if;
      when S1 =>
        if input = '1' then
          state <= S1;
          output <= '1';
        else
          state <= S0;
          output <= '0';
        end if;
      when others =>
        state <= S0;
        output <= '0';
    end case;
  end if;
end process;

This VHDL code snippet shows a Mealy machine updating state and output based on input and current state on clock edge.

Execution Table

Step	Current State	Input	Condition	Next State	Output	Action
1	S0	0	input = '1'? No	S0	0	Stay in S0, output 0
2	S0	1	input = '1'? Yes	S1	1	Move to S1, output 1
3	S1	0	input = '1'? No	S0	0	Return to S0, output 0
4	S0	0	input = '1'? No	S0	0	Stay in S0, output 0
5	S0	1	input = '1'? Yes	S1	1	Move to S1, output 1
6	S1	1	input = '1'? Yes	S1	1	Stay in S1, output 1
7	S1	0	input = '1'? No	S0	0	Return to S0, output 0
8	S0	0	input = '1'? No	S0	0	Stay in S0, output 0
9	S0	End	No more inputs	-	-	Stop execution

💡 No more inputs to process, machine stops.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5	After 6	After 7	After 8	Final
state	S0	S0	S1	S0	S0	S1	S1	S0	S0	S0
input	-	0	1	0	0	1	1	0	0	End
output	-	0	1	0	0	1	1	0	0	-

Key Moments - 2 Insights

Why does the output change immediately when input changes, even before the state updates?

In the Mealy machine, output depends on current state and input together, so output updates in the same step as input is read (see execution_table rows 2 and 6).

Why does the state update only on clock edge but output can change immediately?

State updates happen on clock edges (rising_edge(clk)), but output is combinational logic depending on current state and input, so it can change immediately within the clock cycle (see code in execution_sample).

Visual Quiz - 3 Questions

Look at the execution table, what is the output at step 3 when state is S1 and input is 0?

A 1

B -

C 0

D S0

💡 Hint

Check the 'Output' column in execution_table row 3.

At which step does the state first change from S0 to S1?

A Step 1

B Step 2

C Step 3

D Step 5

💡 Hint

Look at the 'Next State' column in execution_table rows 1 and 2.

If the input at step 6 was changed from '1' to '0', what would be the next state?

A S0

B S1

C S2

D No change

💡 Hint

Refer to the condition and next state logic in execution_table row 6.

Concept Snapshot

Mealy Machine in VHDL:
- Output depends on current state and input.
- State updates on clock rising edge.
- Use process with clk and reset.
- Use case statement for states.
- Output assigned inside state and input conditions.
- Output can change immediately with input.

Full Transcript

This visual execution shows a Mealy machine implemented in VHDL. The machine reads input and current state, then decides the next state and output simultaneously. The state updates only on the rising edge of the clock, while the output depends on both the current state and input, allowing it to change immediately. The execution table traces each step with current state, input, condition checked, next state, output, and action taken. The variable tracker shows how state, input, and output change over time. Key moments clarify why output changes immediately and state updates on clock edges. The quiz tests understanding of output values, state transitions, and effects of input changes. The snapshot summarizes the main points for quick reference.

Practice

1.

What is the key characteristic of a Mealy machine in VHDL?

Output depends on:

easy

A. Only next state

B. Only current state

C. Only previous input

D. Current state and current input

Solution

1. Step 1: Understand Mealy machine output logic

   Mealy machine outputs depend on both the current state and the current input signals.

2. Step 2: Compare with other machine types

   Unlike Moore machines, which depend only on the current state, Mealy machines also consider inputs for output.

3. Final Answer:

   Current state and current input -> Option D

4. Quick Check:

   Mealy output = state + input [OK]

Hint: Remember Mealy output changes immediately with input [OK]

Common Mistakes:

• Thinking output depends only on state
• Confusing Mealy with Moore machine
• Ignoring input signals in output logic

2.

Which VHDL code snippet correctly declares a Mealy machine state process sensitive to clock and reset?

process(_____)
begin
  if reset = '1' then
    state <= idle;
  elsif rising_edge(clk) then
    state <= next_state;
  end if;
end process;

easy

A. clk, reset

B. clk

C. reset

D. clk, input

Solution

1. Step 1: Identify signals controlling state updates

   The process must be sensitive to clock and asynchronous reset signals to update state properly.

2. Step 2: Confirm sensitivity list correctness

   Including both clk and reset ensures the process triggers on clock edges and reset changes.

3. Final Answer:

   clk, reset -> Option A

4. Quick Check:

   Sensitivity list = clk + reset [OK]

Hint: State process needs clock and reset sensitivity [OK]

Common Mistakes:

• Omitting reset from sensitivity list
• Including input signals unnecessarily
• Using only clock without reset

3.

Given this Mealy machine output process snippet, what is the output when state = S1 and input = '1'?

process(state, input)
begin
  case state is
    when S0 => output <= '0';
    when S1 =>
      if input = '1' then
        output <= '1';
      else
        output <= '0';
      end if;
    when others => output <= '0';
  end case;
end process;

medium

A. '1'

B. '0'

C. Undefined

D. Error

Solution

1. Step 1: Identify current state and input

   The state is S1 and input is '1'.

2. Step 2: Follow process logic for state S1

   For S1, if input is '1', output is assigned '1'.

3. Final Answer:

   '1' -> Option A

4. Quick Check:

   State S1 + input '1' = output '1' [OK]

Hint: Check state and input conditions carefully [OK]

Common Mistakes:

• Ignoring input condition inside state
• Assuming output always '0'
• Confusing state names

4.

Identify the error in this Mealy machine next state process:

process(clk, reset)
begin
  if reset = '1' then
    state <= S0;
  elsif rising_edge(clk) then
    case state is
      when S0 => next_state <= S1;
      when S1 => next_state <= S2;
      when others => next_state <= S0;
    end case;
  end if;
end process;

medium

A. Missing input sensitivity in process

B. Assigning next_state inside clocked process

C. Using next_state instead of state for updates

D. No error, code is correct

Solution

1. Step 1: Understand state update logic

   The clocked process should update the current state, not next_state.

2. Step 2: Identify incorrect assignment

   Assigning next_state inside the clocked process is incorrect; state must be updated on clock edge.

3. Final Answer:

   Assigning next_state inside clocked process -> Option B

4. Quick Check:

   Clocked process updates state, not next_state [OK]

Hint: Update current state on clock, next_state in combinational [OK]

Common Mistakes:

• Updating next_state in clocked process
• Confusing state and next_state signals
• Ignoring reset signal

5.

You want to implement a Mealy machine in VHDL that outputs '1' only when the input sequence '101' is detected. Which approach correctly combines state and input for output logic?

hard

A. Use input only in sensitivity list; output depends only on input

B. Use only state in sensitivity list; output depends only on state

C. Use a process with state and input in sensitivity list; output depends on both current state and input

D. Use asynchronous reset to set output directly

Solution

1. Step 1: Understand Mealy machine output requirements

   Output depends on detecting input sequence and current state, so both must be considered.

2. Step 2: Implement output logic in process sensitive to state and input

   Including both in sensitivity list ensures output updates immediately when input or state changes.

3. Step 3: Confirm output depends on current state and input

   This matches Mealy machine behavior for sequence detection.

4. Final Answer:

   Use a process with state and input in sensitivity list; output depends on both current state and input -> Option C

5. Quick Check:

   Output = state + input for sequence detection [OK]

Hint: Output depends on state and input for sequence detection [OK]

Common Mistakes:

• Ignoring input in output logic
• Using Moore machine style output
• Relying only on asynchronous reset for output