Process sensitivity list in VHDL

Introduction

A process sensitivity list tells VHDL which signals to watch. When any signal in the list changes, the process runs. This helps the circuit react only when needed.

When you want to run some code only when certain signals change.

When modeling combinational logic that depends on inputs.

When you want to avoid running a process unnecessarily to save simulation time.

When you want to describe hardware behavior that reacts to signal changes.

When you want to create a clocked process that reacts to a clock signal.

Syntax

VHDL

process (signal1, signal2, ...)
begin
    -- sequential statements
end process;

The signals inside the parentheses form the sensitivity list.

The process runs only when any signal in the list changes value.

Examples

This process runs whenever a or b changes, updating c.

VHDL

process (a, b)
begin
    c <= a and b;
end process;

This process runs only on changes of clk, typically a clock signal.

VHDL

process (clk)
begin
    if rising_edge(clk) then
        q <= d;
    end if;
end process;

This process runs when reset changes, to reset q.

VHDL

process (reset)
begin
    if reset = '1' then
        q <= '0';
    end if;
end process;

A process without a sensitivity list runs only once at simulation start or waits indefinitely.

VHDL

process
begin
    -- no sensitivity list means this process runs once at start
    wait;
end process;

Sample Program

This VHDL code defines a simple circuit where output c updates whenever inputs a or b change. The process sensitivity list contains a and b, so the process runs only when one of these signals changes.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity sensitivity_example is
    port (
        a : in std_logic;
        b : in std_logic;
        c : out std_logic
    );
end sensitivity_example;

architecture behavior of sensitivity_example is
begin
    process (a, b)
    begin
        c <= a or b;
    end process;
end behavior;

Important Notes

Time complexity is not applicable as this is hardware description, but simulation efficiency improves by limiting sensitivity list to needed signals.

Common mistake: forgetting to include all signals that affect outputs in the sensitivity list, causing simulation mismatches.

Use sensitivity lists for combinational logic. For clocked logic, use only the clock (and reset if needed) in the sensitivity list.

Summary

A process sensitivity list controls when the process runs by listing signals to watch.

Include all signals that affect the process outputs to avoid simulation errors.

Use sensitivity lists to model combinational or clocked logic efficiently.

Practice

1. What does the sensitivity list in a VHDL process specify?

easy

A. Which signals trigger the process to run when they change

B. The order in which signals are assigned values

C. The data types of signals inside the process

D. The clock frequency for the process execution

Solution

1. Step 1: Understand the role of sensitivity list

   The sensitivity list tells VHDL which signals to watch for changes.

2. Step 2: Identify what triggers the process

   The process runs only when a signal in the sensitivity list changes value.

3. Final Answer:

   Which signals trigger the process to run when they change -> Option A

4. Quick Check:

   Sensitivity list = triggers process run [OK]

Hint: Sensitivity list = signals that start the process [OK]

Common Mistakes:

• Thinking sensitivity list sets signal data types
• Confusing sensitivity list with signal assignment order
• Assuming sensitivity list controls clock frequency

2. Which of the following is the correct syntax for a process sensitivity list in VHDL?

easy

A. process {clk, reset}

B. process clk, reset

C. process [clk, reset]

D. process(clk, reset)

Solution

1. Step 1: Recall VHDL process syntax

   The sensitivity list is enclosed in parentheses after the keyword process.

2. Step 2: Match correct syntax

   Only the syntax with parentheses and comma-separated signals is correct: process(clk, reset)

3. Final Answer:

   process(clk, reset) -> Option D

4. Quick Check:

   Parentheses and commas = correct syntax [OK]

Hint: Use parentheses with commas for sensitivity list [OK]

Common Mistakes:

• Omitting parentheses around sensitivity list
• Using square or curly brackets instead of parentheses
• Separating signals with spaces instead of commas

3. Consider this VHDL process:

process(a, b)
begin
  c <= a and b;
end process;

What happens if signal b changes value?

medium

A. The process does not run because only a triggers it

B. The process runs and updates c

C. The process runs but c remains unchanged

D. The process causes a syntax error

Solution

1. Step 1: Check sensitivity list signals

   The process sensitivity list includes signals a and b.

2. Step 2: Understand process triggering

   When b changes, the process runs and updates c with a and b.

3. Final Answer:

   The process runs and updates c -> Option B

4. Quick Check:

   Signal in sensitivity list changed = process runs [OK]

Hint: Process runs when any sensitivity signal changes [OK]

Common Mistakes:

• Thinking only first signal triggers process
• Assuming process runs but output doesn't update
• Confusing syntax error with normal behavior

4. Identify the error in this VHDL process:

process(clk)
begin
  if reset = '1' then
    q <= '0';
  elsif rising_edge(clk) then
    q <= d;
  end if;
end process;

Assuming reset is a signal, what is the problem?

medium

A. Reset signal is missing from the sensitivity list

B. Clock signal should not be in the sensitivity list

C. The process should use falling_edge instead of rising_edge

D. The process syntax is correct with no errors

Solution

1. Step 1: Check signals used inside process

   The process uses reset and clk signals.

2. Step 2: Verify sensitivity list completeness

   Only clk is in the sensitivity list; reset is missing, which can cause simulation mismatches.

3. Final Answer:

   Reset signal is missing from the sensitivity list -> Option A

4. Quick Check:

   All input signals must be in sensitivity list [OK]

Hint: Include all input signals in sensitivity list [OK]

Common Mistakes:

• Ignoring signals that affect outputs in sensitivity list
• Thinking clock should be removed from sensitivity list
• Confusing edge detection with sensitivity list content

5. You have a process sensitive to signals a and b. Inside, you compute c <= a or b;. Later, you add a new signal enable that gates the output: if enable = '1' then c <= a or b; else c <= '0'; end if;
What must you do to the sensitivity list to ensure correct simulation?

hard

A. Remove a and b from the sensitivity list

B. No change needed; sensitivity list stays the same

C. Add enable to the sensitivity list

D. Replace sensitivity list with only enable

Solution

1. Step 1: Identify all signals affecting outputs

   Now enable controls output c along with a and b.

2. Step 2: Update sensitivity list accordingly

   To simulate correctly, enable must be added to the sensitivity list with a and b.

3. Final Answer:

   Add enable to the sensitivity list -> Option C

4. Quick Check:

   All input signals in sensitivity list = correct simulation [OK]

Hint: Add all signals that affect outputs to sensitivity list [OK]

Common Mistakes:

• Forgetting to add new control signals to sensitivity list
• Removing original signals from sensitivity list incorrectly
• Assuming sensitivity list auto-updates with code changes