Three-process FSM coding style in VHDL

Introduction

A three-process FSM style helps organize your digital design clearly by separating state memory, next state logic, and output logic.

When designing a digital circuit that changes behavior based on inputs over time.

When you want your design to be easy to read and debug by splitting tasks.

When you need to clearly separate how states change and how outputs are generated.

When working on FPGA or ASIC designs that use finite state machines.

When you want to follow a common, structured coding style for FSMs.

Syntax

VHDL

process(clk, reset)
begin
  if reset = '1' then
    current_state <= initial_state;
  elsif rising_edge(clk) then
    current_state <= next_state;
  end if;
end process;

process(current_state, inputs)
begin
  case current_state is
    when state1 =>
      if condition then
        next_state <= state2;
      else
        next_state <= state1;
      end if;
    when others =>
      next_state <= state1;
  end case;
end process;

process(current_state, inputs)
begin
  case current_state is
    when state1 =>
      output_signal <= '0';
    when state2 =>
      output_signal <= '1';
    when others =>
      output_signal <= '0';
  end case;
end process;

The first process handles state updates on clock edges and reset.

The second process decides the next state based on current state and inputs.

Examples

This process updates the current state on the clock's rising edge or resets it.

VHDL

process(clk, reset)
begin
  if reset = '1' then
    current_state <= IDLE;
  elsif rising_edge(clk) then
    current_state <= next_state;
  end if;
end process;

This process decides the next state based on the current state and input signal start.

VHDL

process(current_state, start)
begin
  case current_state is
    when IDLE =>
      if start = '1' then
        next_state <= RUNNING;
      else
        next_state <= IDLE;
      end if;
    when RUNNING =>
      next_state <= IDLE;
    when others =>
      next_state <= IDLE;
  end case;
end process;

This process sets the output led depending on the current state.

VHDL

process(current_state)
begin
  case current_state is
    when IDLE =>
      led <= '0';
    when RUNNING =>
      led <= '1';
    when others =>
      led <= '0';
  end case;
end process;

Sample Program

This VHDL program shows a simple FSM with two states: IDLE and RUNNING. The FSM changes state when start is '1'. The output led turns on in RUNNING state and off in IDLE.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity fsm_example is
  port(
    clk : in std_logic;
    reset : in std_logic;
    start : in std_logic;
    led : out std_logic
  );
end entity;

architecture behavioral of fsm_example is
  type state_type is (IDLE, RUNNING);
  signal current_state, next_state : state_type;
begin
  -- State register process
  process(clk, reset)
  begin
    if reset = '1' then
      current_state <= IDLE;
    elsif rising_edge(clk) then
      current_state <= next_state;
    end if;
  end process;

  -- Next state logic process
  process(current_state, start)
  begin
    case current_state is
      when IDLE =>
        if start = '1' then
          next_state <= RUNNING;
        else
          next_state <= IDLE;
        end if;
      when RUNNING =>
        next_state <= IDLE;
      when others =>
        next_state <= IDLE;
    end case;
  end process;

  -- Output logic process
  process(current_state)
  begin
    case current_state is
      when IDLE =>
        led <= '0';
      when RUNNING =>
        led <= '1';
      when others =>
        led <= '0';
    end case;
  end process;
end architecture;

Important Notes

Make sure to include all signals in the sensitivity list for combinational processes.

Use meaningful state names to keep your code readable.

Resetting the state helps start your FSM in a known condition.

Summary

Three-process FSM style splits state update, next state logic, and output logic into separate processes.

This style makes your design easier to understand and maintain.

It is a common and recommended way to write FSMs in VHDL.

Practice

1. In the three-process FSM coding style in VHDL, which process is responsible for storing the current state?

easy

A. The next state logic process

B. The state register process

C. The output logic process

D. The clock generation process

Solution

1. Step 1: Understand the role of each process

   The three-process FSM style divides the FSM into state register, next state logic, and output logic processes.

2. Step 2: Identify which process stores the current state

   The state register process updates and stores the current state on clock edges.

3. Final Answer:

   The state register process -> Option B

4. Quick Check:

   State storage = state register process [OK]

Hint: State storage always happens in the state register process [OK]

Common Mistakes:

• Confusing next state logic with state storage
• Thinking output logic stores the state
• Assuming clock generation is part of FSM

2. Which of the following is the correct sensitivity list for the next state logic process in a three-process FSM?

easy

A. clk, reset

B. clk

C. outputs

D. current_state, inputs

Solution

1. Step 1: Recall what next state logic depends on

   The next state logic calculates the next state based on the current state and inputs.

2. Step 2: Determine the sensitivity list

   It must react to changes in current_state and inputs, so these go in the sensitivity list.

3. Final Answer:

   current_state, inputs -> Option D

4. Quick Check:

   Next state logic sensitivity = current_state, inputs [OK]

Hint: Next state logic sensitive to current state and inputs only [OK]

Common Mistakes:

• Including clk in next state logic sensitivity list
• Using outputs in sensitivity list
• Leaving sensitivity list empty

3. Given the following partial FSM code snippet, what will be the output value of output_signal when current_state is S1 and input_signal is '1'?

process(current_state, input_signal)
begin
  case current_state is
    when S0 => output_signal <= '0';
    when S1 =>
      if input_signal = '1' then
        output_signal <= '1';
      else
        output_signal <= '0';
      end if;
    when others => output_signal <= '0';
  end case;
end process;

medium

A. Undefined

B. '0'

C. '1'

D. Signal retains previous value

Solution

1. Step 1: Analyze the output logic for state S1

   When current_state is S1, output_signal is '1' if input_signal is '1', else '0'.

2. Step 2: Apply given inputs

   current_state = S1 and input_signal = '1' means output_signal <= '1'.

3. Final Answer:

   '1' -> Option C

4. Quick Check:

   Output for S1 with input '1' = '1' [OK]

Hint: Check state and input conditions carefully for output logic [OK]

Common Mistakes:

• Ignoring input condition inside S1
• Assuming output is always '0' in S1
• Confusing output logic with next state logic

4. Identify the error in this state register process code snippet for a three-process FSM:

process(clk, reset)
begin
  if reset = '1' then
    current_state <= S0;
  elsif rising_edge(clk) then
    next_state <= current_state;
  end if;
end process;

medium

A. Using next_state instead of current_state on clock edge

B. Missing sensitivity to next_state signal

C. Reset condition should be inside rising_edge(clk)

D. No error, code is correct

Solution

1. Step 1: Understand state register role

   The state register updates current_state with next_state on clock edge.

2. Step 2: Check assignment inside clock edge

   The code assigns next_state <= current_state, which is reversed and wrong.

3. Final Answer:

   Using next_state instead of current_state on clock edge -> Option A

4. Quick Check:

   State register updates current_state, not next_state [OK]

Hint: State register updates current_state from next_state [OK]

Common Mistakes:

• Assigning next_state inside state register process
• Placing reset inside clock edge condition
• Confusing current_state and next_state signals

5. You want to design a three-process FSM with states IDLE, BUSY, and DONE. Which of the following correctly describes the responsibilities of the three processes?

hard

A. Process 1: Store current state; Process 2: Compute next state from current state and inputs; Process 3: Generate outputs based on current state

B. Process 1: Generate outputs; Process 2: Store current state; Process 3: Compute next state

C. Process 1: Compute next state; Process 2: Generate outputs; Process 3: Store current state

D. Process 1: Store current state and outputs; Process 2: Compute next state; Process 3: Reset FSM

Solution

1. Step 1: Recall three-process FSM roles

   The three processes are: state register (store current state), next state logic (compute next state), output logic (generate outputs).

2. Step 2: Match roles to options

   Process 1: Store current state; Process 2: Compute next state from current state and inputs; Process 3: Generate outputs based on current state correctly assigns these roles in order.

3. Final Answer:

   Process 1: Store current state; Process 2: Compute next state from current state and inputs; Process 3: Generate outputs based on current state -> Option A

4. Quick Check:

   Three-process FSM roles = B [OK]

Hint: Remember: register stores state, logic computes next, output drives signals [OK]

Common Mistakes:

• Mixing output generation with state storage
• Assigning reset to a separate process
• Combining multiple roles in one process