Why process is used for sequential logic in VHDL

Introduction

A process in VHDL helps us write steps that happen one after another, like following a recipe. It is used to describe sequential logic where order matters.

When you want to describe a set of actions that happen in sequence, like a clocked circuit.

When you need to store values and update them step-by-step.

When you want to model flip-flops or registers that change on clock edges.

When you want to write code that depends on previous steps or states.

When you want to control timing and order of operations in hardware design.

Syntax

VHDL

process (sensitivity_list)
begin
  -- sequential statements here
end process;

The sensitivity_list tells when the process should run, usually signals like clocks or inputs.

Inside the process, statements run one after another, unlike concurrent statements outside.

Examples

This process updates 'q' with 'd' on the rising edge of the clock, modeling a flip-flop.

VHDL

process (clk)
begin
  if rising_edge(clk) then
    q <= d;
  end if;
end process;

This process adds 'a' and 'b' whenever either changes, showing simple sequential logic.

VHDL

process (a, b)
begin
  sum <= a + b;
end process;

Sample Program

This VHDL code uses a process to model a D flip-flop. The process runs on the clock's rising edge and updates output 'q' with input 'd'.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity flip_flop is
  port (
    clk : in std_logic;
    d : in std_logic;
    q : out std_logic
  );
end flip_flop;

architecture behavior of flip_flop is
begin
  process (clk)
  begin
    if rising_edge(clk) then
      q <= d;
    end if;
  end process;
end behavior;

Important Notes

Processes allow you to write code that looks like step-by-step instructions, which is easier to understand for sequential logic.

Without processes, VHDL code is concurrent and runs all statements at once, which is not suitable for sequential behavior.

Summary

Processes are used to describe sequential logic where order and timing matter.

They run when signals in their sensitivity list change, allowing controlled updates.

Inside a process, statements execute one after another, modeling hardware like flip-flops and registers.

Practice

1. Why is a process used in VHDL to describe sequential logic?

easy

A. Because it allows writing step-by-step instructions executed in order

B. Because it automatically creates combinational logic without clocks

C. Because it is used only for defining constants

D. Because it runs only once when the program starts

Solution

1. Step 1: Understand what sequential logic means

   Sequential logic requires instructions to run in a specific order, often controlled by a clock.

2. Step 2: Identify the role of a process in VHDL

   A process allows writing instructions that execute step-by-step when signals change, matching sequential logic needs.

3. Final Answer:

   Because it allows writing step-by-step instructions executed in order -> Option A

4. Quick Check:

   Sequential logic needs ordered steps = process [OK]

Hint: Processes run sequential code stepwise, perfect for clocks [OK]

Common Mistakes:

• Thinking processes run only once
• Confusing processes with combinational logic
• Believing processes define constants only

2. Which of the following is the correct way to start a process block in VHDL for sequential logic?

easy

A. process(clk);

B. process begin(clk)

C. process(clk) begin

D. process(clk) {

Solution

1. Step 1: Recall VHDL process syntax

   A process starts with the keyword process followed by a sensitivity list in parentheses, then begin.

2. Step 2: Check each option for correct syntax

   process(clk) begin matches the correct syntax: process(clk) begin. Others have wrong order, punctuation, or braces not used in VHDL.

3. Final Answer:

   process(clk) begin -> Option C

4. Quick Check:

   Process syntax = process(sensitivity) begin [OK]

Hint: Process starts with 'process(sensitivity) begin' exactly [OK]

Common Mistakes:

• Using semicolon after process header
• Placing sensitivity list after begin
• Using braces {} instead of begin/end

3. What will be the output of the following VHDL process when the clock rises?

process(clk)
begin
  if rising_edge(clk) then
    q <= d;
  end if;
end process;

medium

A. No signal updates because process lacks sensitivity list

B. The signal q updates to the value of d at the rising clock edge

C. The signal q updates continuously without clock

D. The signal d updates to the value of q at the rising clock edge

Solution

1. Step 1: Understand the process sensitivity and condition

   The process triggers on changes to clk. Inside, it checks for a rising edge on clk.

2. Step 2: Analyze the assignment inside the if statement

   When a rising edge occurs, q is assigned the current value of d. This means q updates only at clock rising edges.

3. Final Answer:

   The signal q updates to the value of d at the rising clock edge -> Option B

4. Quick Check:

   rising_edge(clk) triggers q <= d [OK]

Hint: rising_edge(clk) updates q from d only at clock rise [OK]

Common Mistakes:

• Confusing q and d assignment direction
• Thinking q updates continuously
• Ignoring sensitivity list effect

4. Identify the error in this VHDL process for sequential logic:

process(clk)
begin
  if clk = '1' then
    q <= d;
  end if;
end process;

medium

A. Missing rising_edge(clk) check causes incorrect behavior

B. Process sensitivity list is empty

C. Assignment operator <= is invalid inside process

D. Process must use 'wait' statement instead of sensitivity list

Solution

1. Step 1: Review the clock condition inside the process

   The condition if clk = '1' checks level, not edge, so it triggers whenever clk is high, not just on rising edge.

2. Step 2: Understand why rising_edge(clk) is needed

   Sequential logic requires triggering only on clock edges to avoid multiple assignments during clock high level.

3. Final Answer:

   Missing rising_edge(clk) check causes incorrect behavior -> Option A

4. Quick Check:

   Use rising_edge(clk) for correct sequential trigger [OK]

Hint: Use rising_edge(clk) to detect clock edges, not level [OK]

Common Mistakes:

• Using clk = '1' instead of rising_edge(clk)
• Leaving sensitivity list empty
• Confusing assignment operators

5. You want to design a flip-flop that sets output q to '1' on the rising edge of clk only if input set is '1'. Which process structure correctly implements this behavior?

hard

A. process(clk)
begin
q <= '1' when set = '1' else '0';
end process;

B. process(set)
begin
if set = '1' then
q <= '1';
end if;
end process;

C. process(clk)
begin
if clk = '1' then
q <= set;
end if;
end process;

D. process(clk)
begin
if rising_edge(clk) then
if set = '1' then
q <= '1';
end if;
end if;
end process;

Solution

1. Step 1: Identify the clock event trigger

   The flip-flop must update only on the rising edge of clk, so rising_edge(clk) is required.

2. Step 2: Check the condition for setting q

   Inside the clock check, if set = '1' sets q to '1'. This matches the requirement.

3. Step 3: Evaluate other options for correctness

   process(set) begin if set = '1' then q <= '1'; end if; end process; triggers on set changes, not clock edges. process(clk) begin if clk = '1' then q <= set; end if; end process; uses level check, not edge. process(clk) begin q <= '1' when set = '1' else '0'; end process; uses concurrent assignment inside process incorrectly.

4. Final Answer:

   process(clk) begin if rising_edge(clk) then if set = '1' then q <= '1'; end if; end if; end process; -> Option D

5. Quick Check:

   Use rising_edge(clk) and nested if for set condition [OK]

Hint: Nest set check inside rising_edge(clk) for correct flip-flop [OK]

Common Mistakes:

• Triggering on set signal instead of clock
• Using clk = '1' instead of rising_edge(clk)
• Incorrect assignment outside clock check