State type declaration using enumeration in VHDL

Introduction

We use state type declaration with enumeration to name different steps or modes in a process clearly. It helps us control what happens next in a digital circuit.

When designing a traffic light controller with different light phases.

When creating a vending machine that has states like waiting for money, dispensing item, and giving change.

When building a simple elevator control system with states like moving up, moving down, and idle.

When managing communication protocols that have states like idle, sending, and receiving.

Syntax

VHDL

type state_name is (state1, state2, state3, ...);

The type keyword defines a new type.

Enumeration lists all possible states inside parentheses, separated by commas.

Examples

This declares a state type for a traffic light with three states.

VHDL

type traffic_light_state is (red, green, yellow);

This defines states for a vending machine process.

VHDL

type vending_state is (idle, waiting_for_money, dispensing, change_return);

Sample Program

This VHDL code declares a state type with three states: idle, active, and done. It uses these states to control an output signal that changes with each clock cycle.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity simple_fsm is
  port(
    clk : in std_logic;
    reset : in std_logic;
    output_signal : out std_logic
  );
end simple_fsm;

architecture behavior of simple_fsm is
  type state_type is (idle, active, done);
  signal current_state, next_state : state_type := idle;
begin
  process(clk, reset)
  begin
    if reset = '1' then
      current_state <= idle;
    elsif rising_edge(clk) then
      current_state <= next_state;
    end if;
  end process;

  process(current_state)
  begin
    case current_state is
      when idle =>
        output_signal <= '0';
        next_state <= active;
      when active =>
        output_signal <= '1';
        next_state <= done;
      when done =>
        output_signal <= '0';
        next_state <= idle;
      when others =>
        next_state <= idle;
    end case;
  end process;
end behavior;

Important Notes

Enumeration states help make your code easier to read and maintain.

Always include an others clause in case statements to handle unexpected states.

Summary

State type declaration with enumeration names all possible states clearly.

It helps control the flow of digital processes step-by-step.

Using enumerations makes your VHDL code easier to understand and less error-prone.

Practice

1. What is the purpose of declaring a state type using enumeration in VHDL?

easy

A. To define a set of named states for controlling sequential logic

B. To declare variables for arithmetic operations

C. To specify input and output ports

D. To create a loop for iteration

Solution

1. Step 1: Understand state type declaration

   State type declaration using enumeration defines named states that represent different conditions or steps in a process.

2. Step 2: Relate to sequential logic control

   These named states help control the flow of sequential logic circuits like state machines.

3. Final Answer:

   To define a set of named states for controlling sequential logic -> Option A

4. Quick Check:

   State enumeration = named states for control [OK]

Hint: States are named steps controlling sequence flow [OK]

Common Mistakes:

• Confusing state declaration with variable declaration
• Thinking it defines ports or loops
• Assuming it is for arithmetic operations

2. Which of the following is the correct syntax to declare a state type named traffic_light_states with states RED, YELLOW, and GREEN in VHDL?

easy

A. define traffic_light_states as (RED, YELLOW, GREEN);

B. state traffic_light_states = {RED, YELLOW, GREEN};

C. type traffic_light_states is (RED, YELLOW, GREEN);

D. enum traffic_light_states {RED, YELLOW, GREEN};

Solution

1. Step 1: Recall VHDL enumeration syntax

   In VHDL, enumeration types are declared using the keyword type followed by the type name, is, and a list of states in parentheses.

2. Step 2: Match syntax to options

   type traffic_light_states is (RED, YELLOW, GREEN); matches this syntax exactly: type traffic_light_states is (RED, YELLOW, GREEN);

3. Final Answer:

   type traffic_light_states is (RED, YELLOW, GREEN); -> Option C

4. Quick Check:

   VHDL enum syntax = type ... is (...) [OK]

Hint: Use 'type name is (states);' for enumeration [OK]

Common Mistakes:

• Using C or other language syntax like enum or define
• Using curly braces instead of parentheses
• Missing the 'is' keyword

3. Given the following VHDL code snippet:

type state_type is (IDLE, START, RUN, STOP);
signal current_state : state_type := IDLE;

-- Later in process
current_state <= RUN;

What is the value of current_state after the assignment?

medium

A. IDLE

B. RUN

C. START

D. STOP

Solution

1. Step 1: Understand the initial state assignment

   The signal current_state is initially assigned the value IDLE.

2. Step 2: Analyze the state assignment in the process

   Later, current_state is assigned the value RUN, so its value changes to RUN.

3. Final Answer:

   RUN -> Option B

4. Quick Check:

   Assignment changes state to RUN [OK]

Hint: Signal takes assigned enum state value immediately [OK]

Common Mistakes:

• Assuming state remains initial value
• Confusing signal with variable assignment timing
• Choosing a state not assigned

4. Identify the error in the following VHDL state type declaration:

type machine_states is (INIT, RUNNING, PAUSED, STOPPED
signal state : machine_states := INIT;

medium

A. Initial value cannot be assigned to a signal

B. Incorrect keyword 'signal' used for state declaration

C. States should be declared as strings, not identifiers

D. Missing closing parenthesis in the type declaration

Solution

1. Step 1: Check syntax of type declaration

   The enumeration list is missing the closing parenthesis ')' after STOPPED.

2. Step 2: Verify other parts

   The keyword signal is correct for declaring signals, states are identifiers, and initial assignment is allowed.

3. Final Answer:

   Missing closing parenthesis in the type declaration -> Option D

4. Quick Check:

   Parentheses must enclose enum list [OK]

Hint: Check parentheses around enum list carefully [OK]

Common Mistakes:

• Forgetting closing parenthesis
• Misunderstanding signal keyword usage
• Thinking states must be strings

5. You want to declare a state type for a vending machine with states IDLE, SELECT, PAY, DISPENSE, and CHANGE. Which of the following declarations correctly defines this and initializes a signal vm_state to IDLE?

hard

A. type vending_states is (IDLE, SELECT, PAY, DISPENSE, CHANGE);
signal vm_state : vending_states := IDLE;

B. type vending_states is {IDLE, SELECT, PAY, DISPENSE, CHANGE};
signal vm_state : vending_states = IDLE;

C. enum vending_states = (IDLE, SELECT, PAY, DISPENSE, CHANGE);
signal vm_state : vending_states := IDLE;

D. type vending_states is ("IDLE", "SELECT", "PAY", "DISPENSE", "CHANGE");
signal vm_state : vending_states := "IDLE";

Solution

1. Step 1: Confirm correct enumeration syntax

   VHDL uses type name is (state1, state2, ...); with parentheses and no quotes around state names.

2. Step 2: Check signal declaration and initialization

   Signal declaration uses signal name : type := initial_state; with := for initialization.

3. Final Answer:

   type vending_states is (IDLE, SELECT, PAY, DISPENSE, CHANGE); signal vm_state : vending_states := IDLE; -> Option A

4. Quick Check:

   Correct enum syntax + signal init = type vending_states is (IDLE, SELECT, PAY, DISPENSE, CHANGE); signal vm_state : vending_states := IDLE; [OK]

Hint: Use parentheses and no quotes for enum states [OK]

Common Mistakes:

• Using curly braces instead of parentheses
• Using quotes around state names
• Using '=' instead of ':=' for signal initialization