signed and unsigned arithmetic in VHDL

Introduction

Signed and unsigned arithmetic lets you do math with numbers that can be positive or negative (signed) or only positive (unsigned). This helps your digital circuits handle numbers correctly.

When you want to add or subtract numbers that can be negative, like temperatures below zero.

When you only need to work with positive numbers, like counting items or addresses.

When designing digital circuits that process numbers, such as calculators or signal processors.

When converting between different number formats in hardware design.

When you want to avoid errors caused by mixing signed and unsigned numbers.

Syntax

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

signal a, b : signed(7 downto 0);
signal c : unsigned(7 downto 0);
signal result_signed : signed(7 downto 0);
signal result_unsigned : unsigned(7 downto 0);

-- Addition example:
result_signed <= a + b;
result_unsigned <= c + c;

Use signed type for numbers that can be negative.

Use unsigned type for numbers that are always zero or positive.

Examples

This adds two signed 4-bit numbers, one positive and one negative, resulting in zero.

VHDL

signal a : signed(3 downto 0) := "0110"; -- 6 in decimal
signal b : signed(3 downto 0) := "1010"; -- -6 in decimal
signal sum : signed(4 downto 0);
sum <= a + b; -- result is 0

This adds two unsigned 4-bit numbers, both positive, resulting in 8.

VHDL

signal x : unsigned(3 downto 0) := "0101"; -- 5 in decimal
signal y : unsigned(3 downto 0) := "0011"; -- 3 in decimal
signal sum_unsigned : unsigned(4 downto 0);
sum_unsigned <= x + y; -- result is 8

Using to_signed to assign negative and positive values, then adding them.

VHDL

signal a : signed(7 downto 0) := to_signed(-10, 8);
signal b : signed(7 downto 0) := to_signed(20, 8);
signal result : signed(7 downto 0);
result <= a + b; -- result is 10

Sample Program

This program shows adding signed and unsigned numbers. It adds -15 and 10 as signed numbers, and 20 and 5 as unsigned numbers. Then it prints the results.

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity signed_unsigned_example is
end entity;

architecture behavior of signed_unsigned_example is
  signal a : signed(7 downto 0) := to_signed(-15, 8);
  signal b : signed(7 downto 0) := to_signed(10, 8);
  signal c : unsigned(7 downto 0) := to_unsigned(20, 8);
  signal result_signed : signed(7 downto 0);
  signal result_unsigned : unsigned(7 downto 0);
begin
  process
  begin
    result_signed <= a + b; -- -15 + 10 = -5
    result_unsigned <= c + to_unsigned(5, 8); -- 20 + 5 = 25
    wait for 10 ns;
    report "Signed result: " & integer'image(to_integer(result_signed));
    report "Unsigned result: " & integer'image(to_integer(result_unsigned));
    wait;
  end process;
end architecture;

Important Notes

Always use ieee.numeric_std library for signed and unsigned types.

Mixing signed and unsigned types directly can cause errors; convert explicitly if needed.

Remember that signed numbers use two's complement representation internally.

Summary

Signed arithmetic handles positive and negative numbers.

Unsigned arithmetic handles only zero and positive numbers.

Use signed and unsigned types from numeric_std for correct math in VHDL.

Practice

1. Which VHDL type should you use to correctly represent negative numbers in arithmetic operations?

easy

A. unsigned

B. signed

C. std_logic_vector

D. bit_vector

Solution

1. Step 1: Understand number representation types

   Signed types allow representation of both positive and negative numbers, unlike unsigned which only represent zero and positive numbers.

2. Step 2: Identify correct VHDL type for negatives

   In VHDL, the signed type from numeric_std is used for signed arithmetic, supporting negative values.

3. Final Answer:

   signed -> Option B

4. Quick Check:

   Negative numbers need signed type [OK]

Hint: Use signed type for negatives, unsigned for positives only [OK]

Common Mistakes:

• Using unsigned for negative numbers
• Using std_logic_vector without conversion
• Confusing bit_vector with numeric types

2. Which of the following is the correct way to declare a 4-bit unsigned signal in VHDL using numeric_std?

easy

A. signal data : signed(3 downto 0);

B. signal data : bit_vector(3 downto 0);

C. signal data : std_logic_vector(4 downto 0);

D. signal data : unsigned(3 downto 0);

Solution

1. Step 1: Identify the correct type for unsigned 4-bit signal

   The unsigned type from numeric_std is used for unsigned arithmetic and must have 4 bits indexed from 3 downto 0.

2. Step 2: Check each option

   signal data : signed(3 downto 0); uses signed type, which is for signed numbers. signal data : std_logic_vector(4 downto 0); has 5 bits (4 downto 0). signal data : bit_vector(3 downto 0); uses bit_vector, which is not numeric.

3. Final Answer:

   signal data : unsigned(3 downto 0); -> Option D

4. Quick Check:

   Unsigned 4-bit signal uses unsigned(3 downto 0) [OK]

Hint: Unsigned signals use unsigned type with correct bit range [OK]

Common Mistakes:

• Using signed instead of unsigned
• Incorrect bit range (off by one)
• Using std_logic_vector without conversion

3. Given the following VHDL code snippet, what is the decimal value of result after execution?

signal a : signed(3 downto 0) := "1101"; -- -3 in decimal
signal b : unsigned(3 downto 0) := "0011"; -- 3 in decimal
signal result : signed(4 downto 0);

result <= a + signed(resize(b, 5));

medium

A. 0

B. -6

C. 6

D. -3

Solution

1. Step 1: Convert signals to decimal

   a is signed "1101" which is -3 in decimal. b is unsigned "0011" which is 3 in decimal.

2. Step 2: Resize and add values

   b is resized to 5 bits and converted to signed, so 3 remains 3. Adding -3 + 3 = 0.

3. Final Answer:

   0 -> Option A

4. Quick Check:

   -3 + 3 = 0 [OK]

Hint: Convert both to signed before adding, then add values [OK]

Common Mistakes:

• Adding signed and unsigned directly without conversion
• Misinterpreting binary signed values
• Ignoring resize causing wrong bit width

4. Identify the error in the following VHDL code snippet:

signal x : signed(3 downto 0) := "0110";
signal y : unsigned(3 downto 0) := "0011";
signal z : signed(3 downto 0);
z <= x + y;

medium

A. Cannot add signed and unsigned directly without conversion

B. Signal z is declared with wrong bit range

C. Initialization of x is invalid binary

D. No error, code is correct

Solution

1. Step 1: Check types in addition

   In VHDL, you cannot add a signed and an unsigned type directly without converting one to the other's type.

2. Step 2: Identify missing conversion

   The code adds signed x and unsigned y directly, which causes a type mismatch error.

3. Final Answer:

   Cannot add signed and unsigned directly without conversion -> Option A

4. Quick Check:

   Signed + unsigned needs conversion [OK]

Hint: Convert unsigned to signed before adding to signed [OK]

Common Mistakes:

• Adding signed and unsigned without conversion
• Assuming std_logic_vector works for arithmetic
• Ignoring type mismatch errors

5. You want to subtract an unsigned 4-bit number b from a signed 5-bit number a in VHDL. Which is the correct way to perform this operation and store the result in a signed 6-bit signal result?

hard

A. result <= signed(a) - unsigned(b);

B. result <= a - b;

C. result <= resize(a, 6) - signed(resize(b, 6));

D. result <= resize(a, 5) - resize(b, 5);

Solution

1. Step 1: Understand type and size requirements

   To subtract unsigned b from signed a, both must be the same type and size. The result signal is 6 bits signed.

2. Step 2: Convert and resize operands properly

   Resize a to 6 bits signed, convert and resize b to signed 6 bits, then subtract.

3. Final Answer:

   result <= resize(a, 6) - signed(resize(b, 6)); -> Option C

4. Quick Check:

   Resize and convert unsigned to signed before subtracting [OK]

Hint: Resize both and convert unsigned to signed before subtracting [OK]

Common Mistakes:

• Subtracting without resizing operands
• Not converting unsigned to signed before subtraction
• Assigning result to smaller bit width